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STLC3080 PDF预览

STLC3080

更新时间: 2024-11-20 22:42:39
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 模拟传输接口电池电信集成电路电信电路
页数 文件大小 规格书
23页 203K
描述
SUBSCRIBER LINE INTERFACE CIRCUIT

STLC3080 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:10 X 10 MM, 1.40 MM HEIGHT, TQFP-44针数:44
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.8Is Samacsys:N
电池馈电:CONSTANT CURRENT/RESISTIVE电池供电:-48 V
混合:2-4 CONVERSIONJESD-30 代码:S-PQFP-G44
JESD-609代码:e4长度:10 mm
功能数量:1端子数量:44
最高工作温度:85 °C最低工作温度:-40 °C
PSRR-Min:27 dB封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP44,.47SQ,32
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3,5 V
认证状态:Not Qualified座面最大高度:1.6 mm
子类别:Analog Transmission Interfaces最大压摆率:0.0055 mA
标称供电电压:5 V表面贴装:YES
电信集成电路类型:SLIC温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:10 mm
Base Number Matches:1

STLC3080 数据手册

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STLC3080  
SUBSCRIBER LINE INTERFACE CIRCUIT  
PRELIMINARY DATA  
MONOCHIP SLIC SUITABLE FOR PUBLIC  
APPLICATIONS  
IMPLEMENTES ALL KEY FEATURES OF  
THE BORSHT FUNCTION  
DUAL CONTROL MODE CONFIGURATION:  
SLAVE MODE OR AUTOMATIC ACTIVATION  
MODE.  
SOFT BATTERY REVERSAL WITH PRO-  
GRAMMABLE TRANSITION TIME  
ON HOOK TRANSMISSION  
TQFP44 (10 x 10)  
ORDERING NUMBER: STLC3080  
LOOP START/GROUND START FEATURE  
WITH PROGR. THRESHOLD  
LOW POWER DISSIPATION IN ALL OPER-  
ATING MODES  
-40 TO +85°C OPERATING RANGE  
DESCRIPTION  
AUTOMATIC DUAL BATTERY OPERATION  
INTEGRATED RING TRIP DETECTION WITH  
AUTOMATIC AND SYNCRONISED RING  
DISCONNECTION  
METERING PULSE INJECTION  
SURFACE MOUNT PACKAGE  
THREE RELAY DRIVERS FOR RING AND  
TESTING  
The STLC3080 is a SLIC device suitable for a  
wide range of applications: public (CO), transmis-  
sion (DLC) and private (PABX). The SLIC pro-  
vides the standard battery feeding with full pro-  
grammability of the DC characteristic. In particular  
two external resistors allow to set the limiting cur-  
rent value (up to 50mA) and the value of the re-  
sistive feeding when not in constant current re-  
gion.  
BLOCK DIAGRAM  
REL0 REL1 RELR RGND  
CRT RT1 RT2 PCD  
MODE  
D0  
LINE STATUS  
D1  
ILT  
ILL  
TIP  
D2  
LOGIC  
INTERFACE  
SUPERVISION  
LINE  
INTERFACE  
RING  
R0  
COMMANDS  
&
R1  
DECODER  
DET  
GDK/AL  
CSIN  
CSOUT  
CKRING  
RES  
AC+  
DC  
BGND  
VREG  
ILTF  
AC  
DC  
+
TTXIN  
ZB  
REFERENCE  
&
BIAS SWITCHING  
RLIM  
RTH  
AC  
DC  
PROCESSOR  
TX  
PROCESSOR  
RX  
D98TL305B  
ZAC1 ZAC  
RS  
CAC IREF VCC  
VDD AGND CREV CSVR VBAT BASE RDC  
1/23  
December 1999  
This is preliminary information on a new product now in development or undergoing evaluation.  

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