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STLC1511

更新时间： 2024-10-01 22:42:39
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意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
31页 359K
描述
NorthenLite⑩ G.lite BiCMOS Analog Front-End Circuit

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中文翻译

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STLC1511 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：QFP包装说明：10 X 10 MM, 1.40 MM HEIGHT, TQFP-64
针数：64Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.84
JESD-30 代码：S-PQFP-G64JESD-609代码：e4
长度：10 mm功能数量：1
端子数量：64最高工作温度：80 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：LFQFP封装等效代码：QFP64,.47SQ,20
封装形状：SQUARE封装形式：FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
认证状态：Not Qualified座面最大高度：1.6 mm
子类别：Modems标称供电电压：5 V
表面贴装：YES技术：BICMOS
电信集成电路类型：TELECOM CIRCUIT温度等级：OTHER
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：10 mm
Base Number Matches：1

STLC1511 数据手册

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STLC1511  
NorthenLite™ G.lite BiCMOS  
Analog Front-End Circuit  
PRODUCT PREVIEW  
■
Wide transmit (~80dB) and receive (~69dB)  
dynamic range to limit the external filtering  
requirements for extended loop reach operation  
■
■
■
■
■
Programmable tx gain: 0 ÷ -32dB in 2dB steps  
14-bit D/A converter in transmit path  
Programmable rx gain: 0 ÷40dB in 0.5dB steps  
12-bit A/D converter in receive path  
TQFP64  
ORDERING NUMBER: STLC1511  
Integrated phase-locked loop with an externall  
LC or crystal oscillator  
The STLC1511 transmit path consists of a 14-bit  
Nyquist rate D/A converter, followed by a program-  
mable gain amplifier (TxPGA). The transmit gain is  
programmable from 0 to -32dB in 2dB steps.  
■
■
Low power: 300mW @ 5.0V  
64-pin TQFP package  
1.0 GENERAL DESCRIPTION  
The STLC1511 receive path contains a buffer ampli-  
fier followed by a programmable gain amplifier (RxP-  
GA), a low pass anti-aliasing filter, and a 12-bit  
Nyquist rate A/D converter. The RxPGA is digitally  
programmable from 0 to 40dB in 0.5dB steps.  
The STLC1511 G.lite Analog Front End (AFE) chip  
implements the analog transceiver functions required  
in both a central office modem and a customer  
premise modem. It connects the digital modem chip  
with the loop driver and hybrid balance circuits. The  
STLC1511 has been designed with excellent dynam-  
ic range in order to greatly reduce the external filter-  
ing requirements at the front end. The AFE chip and  
its companion digital chip along with a loop driver, im-  
plement the complete G.992.2 DMT modem solution.  
2.0 PACKAGING AND PIN INFORMATION  
2.1 STLC1511 Pin Allocation  
The pinout for the STLC1511 is depicted in Figure 1.  
Figure 1. STLC1511 pinout  
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49  
1
2
3
4
5
6
7
8
9
VDDDIG1  
CK35M  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
QVEEBIAS  
VEEBIAS  
VCCBIAS  
IREF50m  
V3P75V  
VCCPLL  
VEEPLL  
FREQ  
DIGREF  
RXSOUT[0]  
RXSOUT[1]  
VSSDIGE1  
VSSDIG2  
VDDDIGE1  
VDDDIG2  
DTX  
OSCNE  
OSCNB  
OSCPB  
OSCPE  
VCAP  
10  
11  
12  
13  
14  
DIGCLK  
ENB  
DRX  
VEEADC  
VCCADC  
QVEEADC  
VDDPLL  
VSSPLL  
QVEEPLL  
15  
16  
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32  
TQFP64  
November 2000  
1/31  
This is preliminary information on a new product now in development. Details are subject to change without notice.  
1234567...31

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