Datasheet > STK12C68-5

STK12C68-5

更新时间： 2022-12-23 03:42:49

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		存储静态存储器
页数	文件大小	规格书
18页	575K
描述
64 Kbit (8K x 8) AutoStore nvSRAM

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数据手册

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STK12C68-5 数据手册

STK12C68-5 (SMD5962-94599)

Software Controlled STORE/RECALL Cycle

The software controlled STORE/RECALL cycle follows. ^[18]

35 ns

55 ns

Max

Parameter

Alt

Description

Unit

Min

Max

Min

[14]

t_RC

t_AVAV

t_AVEL

t_ELEH

t_ELAX

STORE/RECALL Initiation Cycle Time

Address Setup Time

μs

[17]

t_SA

[17]

t_CW

Clock Pulse Width

[17]

t_HACE

Address Hold Time

t_RECALL

RECALL Duration

Switching Waveform

Figure 13. CE Controlled Software STORE/RECALL Cycle ^[18]

t_RC

ADDRESS # 1

ADDRESS # 6

ADDRESS

t_SA

t_SCE

t_HACE

_STORE/ t_RECALL

HIGH IMPEDANCE

DATA VALID

DQ (DATA)

Notes

17. The software sequence is clocked on the falling edge of CE without involving OE (double clocking aborts the sequence).

18. The six consecutive addresses must be read in the order listed in Table 1 on page 6. WE must be HIGH during all six consecutive cycles.

Document Number: 001-51026 Rev. **

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STK12C68-5C25M	ETC	8K x 8 AutoStore⑩ nvSRAM QuantumTrap⑩ CMOS No	获取价格
STK12C68-5C30	CYPRESS	8KX8 NON-VOLATILE SRAM, 30ns, CDIP28, 0.300 INCH, CERAMIC, DIP-28	获取价格
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