November 2001
SSR1N60B / SSU1N60B
600V N-Channel MOSFET
General Description
Features
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for high efficiency switch mode power supplies.
•
•
•
•
•
•
0.9A, 600V, R
= 12Ω @V = 10 V
DS(on) GS
Low gate charge ( typical 5.9 nC)
Low Crss ( typical 3.6 pF)
Fast switching
100% avalanche tested
Improved dv/dt capability
D
!
D
●
◀
▲
●
●
!
G
I-PAK
SSU Series
D-PAK
SSR Series
G
S
G D S
!
S
Absolute Maximum Ratings
T = 25°C unless otherwise noted
C
Symbol
Parameter
SSR1N60B / SSU1N60B
Units
V
V
I
Drain-Source Voltage
600
0.9
DSS
- Continuous (T = 25°C)
Drain Current
A
D
C
- Continuous (T = 100°C)
0.57
3.0
A
C
I
(Note 1)
Drain Current
- Pulsed
A
DM
V
E
I
Gate-Source Voltage
± 30
50
V
GSS
AS
(Note 2)
(Note 1)
(Note 1)
(Note 3)
Single Pulsed Avalanche Energy
Avalanche Current
mJ
A
0.9
AR
E
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
2.8
mJ
V/ns
W
AR
dv/dt
5.5
Power Dissipation (T = 25°C) *
2.5
P
A
D
Power Dissipation (T = 25°C)
28
W
C
- Derate above 25°C
Operating and Storage Temperature Range
0.22
-55 to +150
W/°C
°C
T , T
J
stg
Maximum lead temperature for soldering purposes,
T
300
°C
L
1/8" from case for 5 seconds
Thermal Characteristics
Symbol
Parameter
Typ
--
Max
4.53
50
Units
°C/W
°C/W
°C/W
R
R
R
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient *
Thermal Resistance, Junction-to-Ambient
θJC
θJA
θJA
--
--
110
* When mounted on the minimum pad size recommended (PCB Mount)
©2001 Fairchild Semiconductor Corporation
Rev. B, November 2001