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SST5198NL

更新时间： 2024-10-27 06:14:23
品牌 Logo 应用领域
威世 - VISHAY 晶体小信号场效应晶体管
页数 文件大小 规格书
6页 70K
描述
Monolithic N-Channel JFET Duals

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中文翻译

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SST5198NL 技术参数

生命周期：Obsolete包装说明：,
Reach Compliance Code：unknown风险等级：5.84
Is Samacsys：NFET 技术：JUNCTION
最高工作温度：150 °C极性/信道类型：N-CHANNEL
最大功率耗散 (Abs)：0.5 W子类别：FET General Purpose Small Signal
表面贴装：YESBase Number Matches：1

SST5198NL 数据手册

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SST/U5196NL Series  
New Product  
Vishay Siliconix  
Monolithic N-Channel JFET Duals  
SST5198NL  
SST5199NL  
U5196NL  
U5197NL  
U5198NL  
U5199NL  
PRODUCT SUMMARY  
Part Number VGS(off) (V) V(BR)GSS Min (V) gfs Min (mS) IG Max (pA) ꢀ VGS1 - VGS2ꢀ Max (mV)  
U5196NL  
U5197NL  
-0.7 to -4  
-0.7 to -4  
-0.7 to -4  
-0.7 to -4  
-50  
-50  
-50  
-50  
1
1
1
1
-15  
-15  
-15  
-15  
5
5
SST/U5198NL  
SST/U5199NL  
10  
15  
FEATURES  
BENEFITS  
APPLICATIONS  
D Anti Latchup Capability  
D Monolithic Design  
D High Slew Rate  
D External Substrate Bias—Avoids Latchup  
D Tight Differential Match vs. Current  
D Improved Op Amp Speed, Settling Time Accuracy  
D Minimum Input Error/Trimming Requirement  
D Insignificant Signal Loss/Error Voltage  
D High System Sensitivity  
D Wideband Differential Amps  
D High-Speed, Temp-Compensated,  
Single-Ended Input Amps  
D High Speed Comparators  
D Low Offset/Drift Voltage  
D Low Gate Leakage: 5 pA  
D Low Noise  
D Impedance Converters  
D High CMRR: 100 dB  
D Minimum Error with Large Input Signal  
DESCRIPTION  
The SST/U5196NL series of JFET duals are designed for  
high-performance differential amplification for a wide range of  
precision test instrumentation applications. This series  
features tightly matched specs, low gate leakage for accuracy,  
and wide dynamic range with IG guaranteed at VDG = 20 V.  
The U series in the hermetically-sealed TO-78 package is  
available with full military processing. The SST series SO-8  
package provides ease of manufacturing and the symmetrical  
pinout prevents improper orientation. The SO-8 package is  
available with tape-and-reel options for compatibility with  
automatic assembly methods.  
Pins 4 and 8 of the SST series and pin 4 on the U series part  
numbers enable the substrate to be connected to a positive,  
external bias (VDD) to avoid latchup.  
For similar products see the low-noise SST/U401NL series  
and the low-leakage U421NL/423NL data sheets.  
TO-78  
Narrow Body SOIC  
S
D
G
SUBSTRATE  
1
2
3
4
8
7
6
5
1
1
1
S
G
2
1
G
2
1
3
7
5
D
2
D
1
D
2
SUBSTRATE  
S
2
2
6
Top View  
G
1
S
2
4
Marking Codes:  
CASE, SUBSTRATE  
Top View  
SST5198NL - 5198NL  
SST5199NL - 5199NL  
U5196NL, U5198NL  
U5197NL, U5199NL  
ABSOLUTE MAXIMUM RATINGS  
a
Gate-Drain, Gate-Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 V  
Gate Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA  
Power Dissipation :  
Notes  
Per Side . . . . . . . . . . . . . . . . . . . . . . . . 250 mW  
b
Total . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mW  
1
Lead Temperature ( / ” from case for 10 sec.) . . . . . . . . . . . . . . . . . . 300 _C  
16  
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 200_C  
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -55 to 150_C  
a. Derate 2 mW/_C above 85_C  
b. Derate 4 mW/_C above 85_C  
Document Number: 72156  
S-03468—Rev. B, 11-Mar-03  
www.vishay.com  
7-1  
123456

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