16 Mbit LPC Serial Flash
SST49LF016C
016C16Mb LPC Firmware Flash
Data Sheet
FEATURES:
•
Operational Clock Frequency
– 33 MHz
– 66 MHz
•
•
Two-cycle Command Set
Security ID Feature
– 256-bit Secure ID space
•
•
Organized as 2M x8
Conforms to LPC Interface Specification v1.1
– Support Multi-Byte Firmware Memory Read/
Write Cycles
Single 3.0-3.6V Read and Write Operations
LPC Mode
– 5-signal LPC bus interface for both in-system
and factory programming using programmer
equipment
– Multi-Byte Read data transfer rate
15.6 MB/s @ 33 MHz PCI clock and
31.2 MB/s @ 66 MHz clock
- 64-bit Unique Factory Pre-programmed
Device Identifier
- 192-bit User-Programmable OTP
•
•
•
Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
•
•
Low Power Consumption
– Active Read Current: 12 mA (typical)
– Standby Current: 10 µA (typical)
Uniform 4 KByte sectors
– 35 Overlay Blocks: one 16-KByte Boot Block,
two 8-KByte Parameter Blocks, one 32-Kbyte
Parameter Block, thirty-one 64-KByte Main
Blocks.
- Firmware Memory Read cycle supporting
1, 2, 4, 16, and 128 Byte Read
- Firmware Memory Write cycle supporting
1, 2, and 4 Byte Write
•
•
Fast Sector-Erase/Program Operation
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Program Time: 7 µs (typical)
– 33 MHz/66 MHz clock frequency operation
– WP#/AAI and TBL# pins provide hardware Write
protect for entire chip and/or top Boot Block
– Block Locking Registers for individual block Read-
Lock, Write-Lock, and Lock-Down protection
– 5 GPI pins for system design flexibility
– 4 ID pins for multi-chip selection
– Multi-Byte capability registers
Auto Address Increment (AAI) for Rapid Factory
Programming (High Voltage Enabled)
– RY/BY# pin for End-of-Write detection
– Multi-Byte Program
– Chip Rewrite Time: 4 seconds (typical)
Packages Available
– 32-lead PLCC
– 32-lead TSOP (8mm x 14mm)
All non-Pb (lead-free) devices are RoHS compliant
(read-only registers)
– Status register for End-of-Write detection
– Program-/Erase-Suspend
•
•
Read or Write to other blocks during
Program-/Erase-Suspend
PRODUCT DESCRIPTION
The SST49LF016C flash memory device is designed to
interface with host controllers (chipsets) that support a low-
pin-count (LPC) interface for system firmware applications.
Complying with LPC Interface Specification 1.1,
SST49LF016C supports a Burst-Read data transfer of
15.6 MBytes per second at 33 MHz clock speed and 31.2
MBytes per second at 66 MHz clock speed, up to 128
bytes in a single operation.
Via the software registers, the SST49LF016C offers hard-
ware block protection and individual block protection for crit-
ical system code and data. The 256-bit Security ID space is
comprised of a 64-bit factory pre-programmed unique
number and a 192-bit One-Time-Programmable (OTP)
area. This Security ID permits the use of new security tech-
niques and implementation of a new data protection
scheme. To protect against inadvertent write, the
SST49LF016C device has on-chip hardware and software
write protection schemes. The SST49LF016C also pro-
vides general purpose inputs (GPI) for system design flexi-
bility.
The LPC interface operates with 5 signal pins versus 28
pins of a 8-bit parallel flash memory. This frees up pins on
the ASIC host controller resulting in lower ASIC costs and a
reduction in overall system costs due to simplified signal
routing. This 5-signal LPC interface supports both in-sys-
tem and rapid factory programming using programmer
equipment. A high voltage pin (WP#/AAI) enables Auto
Address Increment (AAI) mode.
Manufactured with SST proprietary, high-performance
SuperFlash technology, SST49LF016C has a split-gate cell
design and thick-oxide tunneling injector for greater reliabil-
ity and manufacturability compared with alternative technol-
ogy approaches.
©2006 Silicon Storage Technology, Inc.
The SST logo and SuperFlash are registered Trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
S71237-07-000
1
9/06
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