8 Mbit LPC Flash
SST49LF080A
Data Sheet
The SST49LF080A flash memory device is designed to interface with the LPC
bus for PC and Internet Appliance application in compliance with Intel Low Pin
Count (LPC) Interface Specification 1.0. Two interface modes are supported: LPC
mode for in-system operations and Parallel Programming (PP) mode to interface
with programming equipment. The SST49LF080A flash memory device is manu-
factured with proprietary, high-performance SuperFlash® Technology. The split-
gate cell design and thick-oxide tunneling injector attain better reliability and man-
ufacturability compared with alternate approaches
Features
• LPC Interface Flash
• Two Operational Modes
– SST49LF080A: 1024K x8 (8 Mbit)
– Low Pin Count (LPC) Interface mode for
in-system operation
• Conforms to Intel LPC Interface Specification 1.0
• Flexible Erase Capability
– Parallel Programming (PP) Mode for fast production pro-
gramming
• LPC Interface Mode
– Uniform 4 KByte Sectors
– 5-signal communication interface supporting byte Read
and Write
– Uniform 64 KByte overlay blocks
– 64 KByte Top Boot Block protection
– Chip-Erase for PP Mode Only
– 33 MHz clock frequency operation
– WP# and TBL# pins provide hardware write protect for
entire chip and/or top boot block
• Single 3.0-3.6V Read and Write Operations
• Superior Reliability
– Standard SDP Command Set
– Data# Polling and Toggle Bit for End-of-Write detection
– 5 GPI pins for system design flexibility
– 4 ID pins for multi-chip selection
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Parallel Programming (PP) Mode
• Low Power Consumption
– 11-pin multiplexed address and 8-pin data
– Active Read Current: 6 mA (typical)
– Standby Current: 10 µA (typical)
I/O interface
– Supports fast programming In-System on
programmer equipment
• Fast Sector-Erase/Byte-Program Operation
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Byte-Program Time: 14 µs (typical)
– Chip Rewrite Time: 16 seconds (typical)
– Single-pulse Program or Erase
– Internal timing generation
• CMOS and PCI I/O Compatibility
• Packages Available
– 32-lead PLCC
– 32-lead TSOP (8mm x 14mm)
• All non-Pb (lead-free) devices are RoHS compliant
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©2014 Silicon Storage Technology, Inc.
DS20005086B
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