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SST39SF040P-55-4C-NH PDF预览

SST39SF040P-55-4C-NH

更新时间： 2024-11-23 21:03:35
品牌 Logo 应用领域
芯科 - SILICON 内存集成电路
页数 文件大小 规格书
28页 280K
描述
Flash, 512KX8, 55ns, PQCC32

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中文翻译

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SST39SF040P-55-4C-NH 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：QCCJ, LDCC32,.5X.6Reach Compliance Code：unknown
风险等级：5.87最长访问时间：55 ns
启动块：BOTTOM/TOP命令用户界面：YES
数据轮询：YESJESD-30 代码：R-PQCC-J32
JESD-609代码：e0内存密度：4194304 bit
内存集成电路类型：FLASH内存宽度：8
部门数/规模：128端子数量：32
字数：524288 words字数代码：512000
最高工作温度：70 °C最低工作温度：
组织：512KX8封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC32,.5X.6
封装形状：RECTANGULAR封装形式：CHIP CARRIER
并行/串行：PARALLEL电源：5 V
认证状态：Not Qualified部门规模：4K
最大待机电流：0.0001 A子类别：Flash Memories
最大压摆率：0.02 mA标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD切换位：YES
类型：NOR TYPEBase Number Matches：1

SST39SF040P-55-4C-NH 数据手册

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2 Mbit / 4 Mbit MPF with Block-Protection  
SST39SF020P / SST39SF040P / SST39VF020P / SST39VF040P  
Preliminary Specifications  
FEATURES:  
•
Fast Erase and Byte-Program:  
•
•
Organized as 256K x8 / 512K x8  
– Sector-Erase Time: 18 ms typical  
– Chip-Erase Time: 70 ms typical  
– Byte-Program Time: 14 µs typical  
– Chip Rewrite Time:  
Single Voltage Read and Write Operations  
1
– 4.5-5.5V for SST39SF020P/040P  
– 2.7-3.6V for SST39VF020P/040P  
4 seconds (typical) for SST39SF/VF020P  
8 seconds (typical) for SST39SF/VF040P  
•
•
Superior Reliability  
2
– Endurance: 100,000 Cycles (typical)  
– Greater than 100 years Data Retention  
•
•
Automatic Write Timing  
– Internal VPP Generation  
End-of-Write Detection  
Low Power Consumption:  
3
– Active Current: 10 mA (typical)  
– Standby Current:  
– Toggle Bit  
– Data# Polling  
30 µA (typical) for SST39SF020P/040P  
1 µA (typical) for SST39VF020P/040P  
4
•
•
•
TTL I/O Compatibility for SST39SF020P/040P  
•
•
•
Sector-Erase Capability  
CMOS I/O Compatibility for SST39VF020P/040P  
– Uniform 4 KByte sectors  
5
JEDEC Standard  
User-Selectable Top or Bottom 16 KByte  
Block -Protection Feature  
– Flash EEPROM Pinouts and command sets  
Packages Available  
•
6
Fast Read Access Time:  
– 32-Pin PDIP  
– 32-Pin PLCC  
– 32-Pin TSOP (8mm x 14mm)  
– 45 and 55 ns for SST39SF020P/040P  
– 70 and 90 ns for SST39VF020P/040P  
7
•
Latched Address and Data  
PRODUCT DESCRIPTION  
the applied voltage, current, and time of application.  
Since for any given voltage range, the SuperFlash  
technology uses less current to program and has a  
shorter erase time, the total energy consumed during  
any Erase or Program operation is less than alternative  
flash technologies. They also improve flexibility while  
lowering the cost for program, data, and configuration  
storage applications.  
8
The SST39SF020P/040P and SST39VF020P/040P  
are 256K x8 / 512K x8 CMOS Multi-Purpose Flash  
(MPF) with Block-Protection manufactured with SST’s  
proprietary, high performance CMOS SuperFlash tech-  
nology.Thesplit-gatecelldesignandthickoxidetunnel-  
ing injector attain better reliability and manufacturability  
compared with alternate approaches. The  
SST39SF020P/040P devices write (Program or Erase)  
with a 4.5-5.5V power supply. The SST39VF020P/  
040P devices write (Program or Erase) with a 2.7-3.6V  
power supply. These devices conform to JEDEC stan-  
dard pinouts for x8 memories.  
9
10  
11  
12  
13  
14  
15  
16  
The SuperFlash technology provides fixed Erase and  
Program times, independent of the number of Erase/  
Program cycles that have occurred. Therefore the sys-  
tem software or hardware does not have to be modified  
or de-rated as is necessary with alternative flash tech-  
nologies, whose Erase and Program times increase  
with accumulated Erase/Program cycles.  
Featuring high performance Byte-Program, the  
SST39SF020P/040P and SST39VF020P/040P de-  
vices provide a maximum Byte-Program time of 20  
µsec.Toprotectagainstinadvertentwrite,theyhaveon-  
chip hardware and Software Data Protection schemes.  
Designed, manufactured, and tested for a wide spec-  
trum of applications, these devices are offered with a  
guaranteed endurance of at least 10,000 cycles. Data  
retention is rated at greater than 100 years.  
To meet high density, surface mount requirements, the  
SST39SF020P/040P and SST39VF020P/040P devices  
areofferedin32-pinTSOPand32-pinPLCCpackages. A  
600 mil, 32-pin PDIP is also offered for SST39SF020P/  
040P devices. See Figures 1, 2 and 3 for pinouts.  
Device Operation  
The SST39SF020P/040P and SST39VF020P/040P  
devices are suited for applications that require conve-  
nient and economical updating of program, configura-  
tion, or data memory. For all system applications, they  
significantly improve performance and reliability, while  
lowering power consumption. They inherently use less  
energy during Erase and Program than alternative flash  
technologies.Thetotalenergyconsumedisafunctionof  
Commands are used to initiate the memory operation  
functions of the device. Commands are written to the  
device using standard microprocessor write se-  
quences. A command is written by asserting WE# low  
while keeping CE# low. The address bus is latched on  
the falling edge of WE# or CE#, whichever occurs last.  
The data bus is latched on the rising edge of WE# or  
CE#, whichever occurs first.  
© 2000 Silicon Storage Technology, Inc.The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF is a trademark of Silicon Storage Technology, Inc.  
501-04 3/00 These specifications are subject to change without notice.  
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