2 Mbit / 4 Mbit MPF with Block-Protection
SST39SF020P / SST39SF040P / SST39VF020P / SST39VF040P
Preliminary Specifications
FEATURES:
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Fast Erase and Byte-Program:
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Organized as 256K x8 / 512K x8
– Sector-Erase Time: 18 ms typical
– Chip-Erase Time: 70 ms typical
– Byte-Program Time: 14 µs typical
– Chip Rewrite Time:
Single Voltage Read and Write Operations
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– 4.5-5.5V for SST39SF020P/040P
– 2.7-3.6V for SST39VF020P/040P
4 seconds (typical) for SST39SF/VF020P
8 seconds (typical) for SST39SF/VF040P
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Superior Reliability
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– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
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Automatic Write Timing
– Internal VPP Generation
End-of-Write Detection
Low Power Consumption:
3
– Active Current: 10 mA (typical)
– Standby Current:
– Toggle Bit
– Data# Polling
30 µA (typical) for SST39SF020P/040P
1 µA (typical) for SST39VF020P/040P
4
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TTL I/O Compatibility for SST39SF020P/040P
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Sector-Erase Capability
CMOS I/O Compatibility for SST39VF020P/040P
– Uniform 4 KByte sectors
5
JEDEC Standard
User-Selectable Top or Bottom 16 KByte
Block -Protection Feature
– Flash EEPROM Pinouts and command sets
Packages Available
•
6
Fast Read Access Time:
– 32-Pin PDIP
– 32-Pin PLCC
– 32-Pin TSOP (8mm x 14mm)
– 45 and 55 ns for SST39SF020P/040P
– 70 and 90 ns for SST39VF020P/040P
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•
Latched Address and Data
PRODUCT DESCRIPTION
the applied voltage, current, and time of application.
Since for any given voltage range, the SuperFlash
technology uses less current to program and has a
shorter erase time, the total energy consumed during
any Erase or Program operation is less than alternative
flash technologies. They also improve flexibility while
lowering the cost for program, data, and configuration
storage applications.
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The SST39SF020P/040P and SST39VF020P/040P
are 256K x8 / 512K x8 CMOS Multi-Purpose Flash
(MPF) with Block-Protection manufactured with SST’s
proprietary, high performance CMOS SuperFlash tech-
nology.Thesplit-gatecelldesignandthickoxidetunnel-
ing injector attain better reliability and manufacturability
compared with alternate approaches. The
SST39SF020P/040P devices write (Program or Erase)
with a 4.5-5.5V power supply. The SST39VF020P/
040P devices write (Program or Erase) with a 2.7-3.6V
power supply. These devices conform to JEDEC stan-
dard pinouts for x8 memories.
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The SuperFlash technology provides fixed Erase and
Program times, independent of the number of Erase/
Program cycles that have occurred. Therefore the sys-
tem software or hardware does not have to be modified
or de-rated as is necessary with alternative flash tech-
nologies, whose Erase and Program times increase
with accumulated Erase/Program cycles.
Featuring high performance Byte-Program, the
SST39SF020P/040P and SST39VF020P/040P de-
vices provide a maximum Byte-Program time of 20
µsec.Toprotectagainstinadvertentwrite,theyhaveon-
chip hardware and Software Data Protection schemes.
Designed, manufactured, and tested for a wide spec-
trum of applications, these devices are offered with a
guaranteed endurance of at least 10,000 cycles. Data
retention is rated at greater than 100 years.
To meet high density, surface mount requirements, the
SST39SF020P/040P and SST39VF020P/040P devices
areofferedin32-pinTSOPand32-pinPLCCpackages. A
600 mil, 32-pin PDIP is also offered for SST39SF020P/
040P devices. See Figures 1, 2 and 3 for pinouts.
Device Operation
The SST39SF020P/040P and SST39VF020P/040P
devices are suited for applications that require conve-
nient and economical updating of program, configura-
tion, or data memory. For all system applications, they
significantly improve performance and reliability, while
lowering power consumption. They inherently use less
energy during Erase and Program than alternative flash
technologies.Thetotalenergyconsumedisafunctionof
Commands are used to initiate the memory operation
functions of the device. Commands are written to the
device using standard microprocessor write se-
quences. A command is written by asserting WE# low
while keeping CE# low. The address bus is latched on
the falling edge of WE# or CE#, whichever occurs last.
The data bus is latched on the rising edge of WE# or
CE#, whichever occurs first.
© 2000 Silicon Storage Technology, Inc.The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF is a trademark of Silicon Storage Technology, Inc.
501-04 3/00 These specifications are subject to change without notice.
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