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SST27SF512-90-3I-NH PDF预览

SST27SF512-90-3I-NH

更新时间： 2024-11-22 15:52:55
品牌 Logo 应用领域
芯科 - SILICON 可编程只读存储器电动程控只读存储器电可擦编程只读存储器内存集成电路
页数 文件大小 规格书
28页 234K
描述
EEPROM, 64KX8, 90ns, Parallel, CMOS, PQCC32

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SST27SF512-90-3I-NH 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：QCCJ, LDCC32,.5X.6Reach Compliance Code：unknown
风险等级：5.92最长访问时间：90 ns
命令用户界面：NO数据轮询：NO
JESD-30 代码：R-PQCC-J32JESD-609代码：e0
内存密度：524288 bit内存集成电路类型：EEPROM
内存宽度：8端子数量：32
字数：65536 words字数代码：64000
最高工作温度：85 °C最低工作温度：-40 °C
组织：64KX8封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC32,.5X.6
封装形状：RECTANGULAR封装形式：CHIP CARRIER
并行/串行：PARALLEL电源：5 V
认证状态：Not Qualified最大待机电流：0.00005 A
子类别：EEPROMs最大压摆率：0.03 mA
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
切换位：NOBase Number Matches：1

SST27SF512-90-3I-NH 数据手册

 浏览型号SST27SF512-90-3I-NH的Datasheet PDF文件第2页浏览型号SST27SF512-90-3I-NH的Datasheet PDF文件第3页浏览型号SST27SF512-90-3I-NH的Datasheet PDF文件第4页浏览型号SST27SF512-90-3I-NH的Datasheet PDF文件第5页浏览型号SST27SF512-90-3I-NH的Datasheet PDF文件第6页浏览型号SST27SF512-90-3I-NH的Datasheet PDF文件第7页 
256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit (x8)  
Many-Time Programmable Flash  
SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020  
Data Sheet  
FEATURES:  
•
Electrical Erase Using Programmer  
•
•
•
Organized as 32K x8 / 64K x8 / 128K x8 / 256K x8  
5.0V (4.5-5.5V) Read Operation  
Superior Reliability  
1
– Does Not Require UV Source  
– Chip-Erase Time: 100 ms (typical)  
•
•
•
•
TTL I/O Compatibility  
2
– Endurance: At least 1000 Cycles  
– Greater than 100 years Data Retention  
JEDEC Standard Byte-wide EPROM Pinouts  
12V Power Supply for Programming/Erase  
Packages Available  
•
Low Power Consumption  
3
– Active Current: 20 mA (typical)  
– Standby Current: 10 µA (typical)  
– 28-Pin PDIP for SST27SF256/512  
– 32-Pin PDIP for SST27SF010/020  
– 32-Pin PLCC  
•
•
Fast Read Access Time  
– 70 and 90 ns  
4
– 32-Pin TSOP (8mm x 14mm)  
Fast Byte-Program Operation  
– Byte-Program Time: 20 µs (typical)  
– Chip-Program Time:  
5
0.7 seconds (typical) for SST27SF256  
1.4 seconds (typical) for SST27SF512  
2.8 seconds (typical) for SST27SF010  
5.6 seconds (typical) for SST27SF020  
6
7
PRODUCT DESCRIPTION  
To meet surface mount and conventional through hole  
requirements, the SST27SF256/512 are offered in 28-  
pinPDIP,32-pinPLCCand32-pinTSOPpackages.The  
SST27SF010/020 are offered in 32-pin PDIP, 32-pin  
PLCC and 32-pin TSOP packages. See Figures 1,2 and  
3 for pinouts.  
The SST27SF256/512/010/020 are a 32K x8 / 64K x8 /  
128K x8 / 256K x8 CMOS, Many-Time Programmable  
(MTP) low cost flash, manufactured with SST’s propri-  
etary, high performance SuperFlash technology. The  
split-gate cell design and thick oxide tunneling injector  
attain better reliability and manufacturability compared  
with alternate approaches. These MTP devices can be  
electrically erased and programmed at least 1000 times  
using an external programmer with a 12 volt power  
supply. They have to be erased prior to programming.  
These devices conform to JEDEC standard pinouts for  
byte-wide memories.  
8
9
10  
11  
12  
13  
14  
15  
16  
Device Operation  
The SST27SF256/512/010/020 are a low cost flash  
solution that can be used to replace existing UV-  
EPROM, OTP, and mask ROM sockets. These devices  
are functionally (read and program) and pin compatible  
with industry standard EPROM products. In addition to  
EPROMfunctionality,thesedevicesalsosupportelectri-  
caleraseoperationviaanexternalprogrammer.Theydo  
not require a UV source to erase, and therefore the  
packages do not have a window.  
Featuring high performance Byte-Program, the  
SST27SF256/512/010/020 provide a Byte-Program  
time of 20 µs. Designed, manufactured, and tested for a  
widespectrumofapplications,thesedevicesareoffered  
withanenduranceofatleast1000cycles.Dataretention  
is rated at greater than 100 years.  
Read  
TheReadoperationoftheSST27SF256/512/010/020is  
controlled by CE# and OE#. Both CE# and OE# have to  
be low for the system to obtain data from the outputs.  
Once the address is stable, the address access time is  
equal to the delay from CE# to output (TCE). Data is  
availableattheoutputafteradelayofTOE fromthefalling  
edge of OE#, assuming that CE# pin has been low and  
The SST27SF256/512/010/020 are suited for applica-  
tions that require infrequent writes and low power non-  
volatile storage. These devices will improve flexibility,  
efficiency, and performance while matching the low cost  
in nonvolatile applications that currently use UV-  
EPROMs, OTPs, and mask ROMs.  
the addresses have been stable for at least TCE - TOE  
.
© 2000 Silicon Storage Technology, Inc.The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MTP is a trademark of Silicon Storage Technology, Inc.  
502-03 2/00 These specifications are subject to change without notice.  
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