4 Megabit (512K x8) SuperFlash EEPROM
SST28SF040A / SST28VF040A
Data Sheet
FEATURES:
•
Single Voltage Read and Write Operations
•
FastReadAccessTime
1
– 5.0V-only for the SST28SF040A
– 2.7-3.6V for the SST28VF040A
– 5.0V-only operation: 90 and 120 ns
– 2.7-3.6V operation: 150 and 200 ns
•
Superior Reliability
•
•
Latched Address and Data
2
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
Hardware and Software Data Protection
– 7-Read-Cycle-SequenceSoftwareData
Protection
•
•
•
MemoryOrganization:512Kx8
Sector-EraseCapability:256BytesperSector
LowPowerConsumption
3
•
End-of-WriteDetection
– Toggle Bit
– Data# Polling
4
– Active Current: 15 mA (typical) for 5.0V and
10 mA (typical) for 2.7-3.6V
– Standby Current: 5 µA (typical)
•
•
TTL I/O Compatibility
JEDEC Standard
5
•
FastSector-Erase/Byte-ProgramOperation
– Flash EEPROM Pinouts
PackagesAvailable
– Byte-Program Time: 35 µs (typical)
– Sector-Erase Time: 2 ms (typical)
– Complete Memory Rewrite: 20 sec (typical)
•
– 32-Pin PDIP
– 32-Pin PLCC
6
– 32-Pin TSOP (8mm x 14mm and 8mm x 20mm)
7
PRODUCTDESCRIPTION
storageofprogram,configuration,ordatamemory.Forall
systemapplications, theSST28SF040A/28VF040Asig-
nificantly improve performance and reliability, while
lowering power consumption when compared with
floppy diskettes or EPROM approaches. Flash
EEPROM technology makes possible convenient and
economical updating of codes and control programs on-
line. The SST28SF040A/28VF040A improve flexibility,
while lowering the cost of program and configuration
storage application.
The SST28SF040A/28VF040A are 512K x8 bit CMOS
Sector-Erase, Byte-Program EEPROMs. The
SST28SF040A/28VF040A are manufactured using
SST’sproprietary,highperformanceCMOSSuperFlash
EEPROM Technology. The split-gate cell design and
thick oxide tunneling injector attain better reliability and
manufacturability compared with alternative ap-
proaches. The SST28SF040A/28VF040A erase and
8
9
10
11
12
13
14
15
16
program with
a single power supply. The
The functional block diagram shows the functional
blocks of the SST28SF040A/28VF040A. Figures 1 and
2 show the pin assignments for the 32 pin TSOP, 32 pin
PDIP, and 32 pin PLCC packages. Pin description and
operation modes are described in Tables 1
through 4.
SST28SF040A/28VF040A conform to JEDEC standard
pinouts for byte wide memories and are compatible with
existing industry standard flash EEPROM pinouts.
Featuring high performance programming, the
SST28SF040A/28VF040A typically Byte-Program in 35
µs. The SST28SF040A/28VF040A typically Sector-
Erase in 2 ms. Both Program and Erase times can be
optimized using interface features such as Toggle bit or
Data# Polling to indicate the completion of the Write
cycle. To protect against an inadvertent write, the
SST28SF040A/28VF040A have on chip hardware and
SoftwareDataProtectionschemes.Designed,manufac-
tured,andtestedforawidespectrumofapplications,the
SST28SF040A/28VF040Aareofferedwithaguaranteed
sector endurance of 104 cycles. Data retention is rated
greater than 100 years.
Device Operation
Commands are used to initiate the memory operation
functions of the device. Commands are written to the
deviceusingstandardmicroprocessorwritesequences.
A command is written by asserting WE# low while
keeping CE# low. The address bus is latched on the
falling edge of WE# or CE#, whichever occurs last. The
data bus is latched on the rising edge of WE# or CE#,
whichever occurs first. Note, during the Software Data
Protection sequence the addresses are latched on the
rising edge of OE# or CE#, whichever occurs first.
The SST28SF040A/28VF040A are best suited for appli-
cations that require reprogrammable nonvolatile mass
©2000 SiliconStorageTechnology,Inc.TheSSTlogoandSuperFlashareregisteredtrademarksofSiliconStorageTechnology,Inc.
SSFisatrademarkofSiliconStorageTechnology,Inc.
Thesespecificationsaresubjecttochangewithoutnotice.
310-3 6/00
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