4 Megabit (512K x 8) SuperFlash EEPROM
SST28SF040 / SST28LF040 / SST28VF040
Data Sheet
FEATURES:
•
Single Voltage Read and Write Operations
•
Fast Read Access Time
1
– 5.0V-only for the SST28SF040
– 3.0-3.6V for the SST28LF040
– 2.7-3.6V for the SST28VF040
– 5.0V-only operation: 120 and 150 ns
– 3.0-3.6V operation: 200 and 250 ns
– 2.7-3.6V operation: 250 and 300 ns
•
Superior Reliability
•
•
Latched Address and Data
2
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
Hardware and Software Data Protection
– 7-Read-Cycle-Sequence Software Data
Protection
3
•
•
•
Memory Organization: 512K x 8
Sector Erase Capability: 256 bytes per Sector
Low Power Consumption
•
End of Write Detection
– Toggle Bit
– Data# Polling
4
– Active Current: 15 mA (typical) for 5.0V and
10 mA (typical) for 3.0-3.6V/2.7-3.6V
– Standby Current: 5 µA (typical)
•
•
TTL I/O Compatibility
5
JEDEC Standard
•
Fast Sector Erase/Byte Program Operation
– Flash EEPROM Pinouts
Packages Available
– Byte Program Time: 35 µs (typical)
– Sector Erase Time: 2 ms (typical)
– Complete Memory Rewrite: 20 sec (typical)
•
6
– 32-Pin PDIP
– 32-Pin PLCC
– 32-Pin TSOP (8mm x 20mm)
7
PRODUCT DESCRIPTION
TheSST28SF040/28LF040/28VF040arebestsuitedfor
applications that require reprogrammable nonvolatile
mass storage of program, configuration, or data
memory. For all system applications, the SST28SF040/
28LF040/28VF040 significantly improve performance
and reliability, while lowering power consumption when
compared with floppy diskettes or EPROM approaches.
EEPROM technology makes possible convenient and
economical updating of codes and control programs on-
line.TheSST28SF040/28LF040/28VF040improveflex-
ibility, while lowering the cost of program and configura-
tion storage application.
8
The SST28SF040/28LF040/28VF040 are 512K x 8 bit
CMOS sector erase, byte program EEPROMs. The
SST28SF040/28LF040/28VF040 are manufactured us-
ing SST’s proprietary, high performance CMOS
SuperFlash EEPROM Technology. The split-gate cell
design and thick oxide tunneling injector attain better
reliability and manufacturability compared with alterna-
tive approaches. The SST28SF040/28LF040/28VF040
erase and program with a single power supply. The
SST28SF040/28LF040/28VF040 conform to JEDEC
standard pinouts for byte wide memories and are com-
patible with existing industry standard EPROM, and
flash EEPROM pinouts.
9
10
11
12
13
14
15
16
The functional block diagram shows the functional
blocks of the SST28SF040/28LF040/28VF040. Figures
1 and 2 show the pin assignments for the 32 pin TSOP,
32pinPDIP,and32pinPLCCpackages.Pindescription
and operation modes are described in Tables 1
through 4.
Featuring high performance programming, the
SST28SF040/28LF040/28VF040typicallybyteprogram
in 35 µs. The SST28SF040/28LF040/28VF040 typically
sector erase in 2 ms. Both program and erase times can
be optimized using interface features such as Toggle bit
or Data# Polling to indicate the completion of the write
cycle. To protect against an inadvertent write, the
SST28SF040/28LF040/28VF040 have on chip hard-
ware and software data protection schemes. Designed,
manufactured,andtestedforawidespectrumofapplica-
tions, the SST28SF040/28LF040/28VF040 are offered
withaguaranteedsectorenduranceof104 or103 cycles.
Data retention is rated greater than 100 years.
Device Operation
Commands are used to initiate the memory operation
functions of the device. Commands are written to the
deviceusingstandardmicroprocessorwritesequences.
A command is written by asserting WE# low while
keeping CE# low. The address bus is latched on the
falling edge of WE# or CE#, whichever occurs last. The
data bus is latched on the rising edge of WE# or CE#,
whichever occurs first. Note, during the software data
protection sequence the addresses are latched on the
rising edge of OE# or CE#, whichever occurs first.
3©0199-0929 S1i/l9ic9on Storage Technology, Inc. The SST logo and SuperFlash are registered trademar1ks of Silicon Storage Technology, Inc. These specifications are subject to change without notice.