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SST28SF040-150-4I-NH PDF预览

SST28SF040-150-4I-NH

更新时间： 2024-09-19 20:06:55
品牌 Logo 应用领域
芯科 - SILICON 内存集成电路
页数 文件大小 规格书
28页 276K
描述
Flash, 512KX8, 150ns, PQCC32

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中文翻译

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SST28SF040-150-4I-NH 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：QCCJ, LDCC32,.5X.6Reach Compliance Code：unknown
风险等级：5.86最长访问时间：150 ns
命令用户界面：NO数据轮询：YES
耐久性：10000 Write/Erase CyclesJESD-30 代码：R-PQCC-J32
JESD-609代码：e0内存密度：4194304 bit
内存集成电路类型：FLASH内存宽度：8
部门数/规模：2K端子数量：32
字数：524288 words字数代码：512000
最高工作温度：85 °C最低工作温度：-40 °C
组织：512KX8封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC32,.5X.6
封装形状：RECTANGULAR封装形式：CHIP CARRIER
并行/串行：PARALLEL电源：5 V
认证状态：Not Qualified部门规模：256
最大待机电流：0.00002 A子类别：Flash Memories
最大压摆率：0.04 mA标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD切换位：YES
类型：NOR TYPEBase Number Matches：1

SST28SF040-150-4I-NH 数据手册

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4 Megabit (512K x 8) SuperFlash EEPROM  
SST28SF040 / SST28LF040 / SST28VF040  
Data Sheet  
FEATURES:  
•
Single Voltage Read and Write Operations  
•
Fast Read Access Time  
1
– 5.0V-only for the SST28SF040  
– 3.0-3.6V for the SST28LF040  
– 2.7-3.6V for the SST28VF040  
– 5.0V-only operation: 120 and 150 ns  
– 3.0-3.6V operation: 200 and 250 ns  
– 2.7-3.6V operation: 250 and 300 ns  
•
Superior Reliability  
•
•
Latched Address and Data  
2
– Endurance: 100,000 Cycles (typical)  
– Greater than 100 years Data Retention  
Hardware and Software Data Protection  
– 7-Read-Cycle-Sequence Software Data  
Protection  
3
•
•
•
Memory Organization: 512K x 8  
Sector Erase Capability: 256 bytes per Sector  
Low Power Consumption  
•
End of Write Detection  
– Toggle Bit  
– Data# Polling  
4
– Active Current: 15 mA (typical) for 5.0V and  
10 mA (typical) for 3.0-3.6V/2.7-3.6V  
– Standby Current: 5 µA (typical)  
•
•
TTL I/O Compatibility  
5
JEDEC Standard  
•
Fast Sector Erase/Byte Program Operation  
– Flash EEPROM Pinouts  
Packages Available  
– Byte Program Time: 35 µs (typical)  
– Sector Erase Time: 2 ms (typical)  
– Complete Memory Rewrite: 20 sec (typical)  
•
6
– 32-Pin PDIP  
– 32-Pin PLCC  
– 32-Pin TSOP (8mm x 20mm)  
7
PRODUCT DESCRIPTION  
TheSST28SF040/28LF040/28VF040arebestsuitedfor  
applications that require reprogrammable nonvolatile  
mass storage of program, configuration, or data  
memory. For all system applications, the SST28SF040/  
28LF040/28VF040 significantly improve performance  
and reliability, while lowering power consumption when  
compared with floppy diskettes or EPROM approaches.  
EEPROM technology makes possible convenient and  
economical updating of codes and control programs on-  
line.TheSST28SF040/28LF040/28VF040improveflex-  
ibility, while lowering the cost of program and configura-  
tion storage application.  
8
The SST28SF040/28LF040/28VF040 are 512K x 8 bit  
CMOS sector erase, byte program EEPROMs. The  
SST28SF040/28LF040/28VF040 are manufactured us-  
ing SST’s proprietary, high performance CMOS  
SuperFlash EEPROM Technology. The split-gate cell  
design and thick oxide tunneling injector attain better  
reliability and manufacturability compared with alterna-  
tive approaches. The SST28SF040/28LF040/28VF040  
erase and program with a single power supply. The  
SST28SF040/28LF040/28VF040 conform to JEDEC  
standard pinouts for byte wide memories and are com-  
patible with existing industry standard EPROM, and  
flash EEPROM pinouts.  
9
10  
11  
12  
13  
14  
15  
16  
The functional block diagram shows the functional  
blocks of the SST28SF040/28LF040/28VF040. Figures  
1 and 2 show the pin assignments for the 32 pin TSOP,  
32pinPDIP,and32pinPLCCpackages.Pindescription  
and operation modes are described in Tables 1  
through 4.  
Featuring high performance programming, the  
SST28SF040/28LF040/28VF040typicallybyteprogram  
in 35 µs. The SST28SF040/28LF040/28VF040 typically  
sector erase in 2 ms. Both program and erase times can  
be optimized using interface features such as Toggle bit  
or Data# Polling to indicate the completion of the write  
cycle. To protect against an inadvertent write, the  
SST28SF040/28LF040/28VF040 have on chip hard-  
ware and software data protection schemes. Designed,  
manufactured,andtestedforawidespectrumofapplica-  
tions, the SST28SF040/28LF040/28VF040 are offered  
withaguaranteedsectorenduranceof104 or103 cycles.  
Data retention is rated greater than 100 years.  
Device Operation  
Commands are used to initiate the memory operation  
functions of the device. Commands are written to the  
deviceusingstandardmicroprocessorwritesequences.  
A command is written by asserting WE# low while  
keeping CE# low. The address bus is latched on the  
falling edge of WE# or CE#, whichever occurs last. The  
data bus is latched on the rising edge of WE# or CE#,  
whichever occurs first. Note, during the software data  
protection sequence the addresses are latched on the  
rising edge of OE# or CE#, whichever occurs first.  
3©0199-0929 S1i/l9ic9on Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice.  
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