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SST27SF256-70-3C-PGE

更新时间： 2024-11-08 15:52:55
品牌 Logo 应用领域
芯科 - SILICON 可编程只读存储器电动程控只读存储器电可擦编程只读存储器光电二极管内存集成电路
页数 文件大小 规格书
28页 339K
描述
Flash, 32KX8, 70ns, PDIP28, LEAD FREE, PLASTIC, MO-015AH, DIP-28

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SST27SF256-70-3C-PGE 技术参数

是否Rohs认证：符合生命周期：Obsolete
零件包装代码：DIP包装说明：DIP, DIP28,.6
针数：28Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.32.00.51
风险等级：5.82Is Samacsys：N
最长访问时间：70 ns命令用户界面：NO
数据轮询：NOJESD-30 代码：R-PDIP-T28
长度：36.83 mm内存密度：262144 bit
内存集成电路类型：FLASH内存宽度：8
功能数量：1端子数量：28
字数：32768 words字数代码：32000
工作模式：ASYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：32KX8
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP28,.6封装形状：RECTANGULAR
封装形式：IN-LINE并行/串行：PARALLEL
电源：5 V编程电压：12 V
认证状态：Not Qualified座面最大高度：5.08 mm
最大待机电流：0.0001 A子类别：EEPROMs
最大压摆率：0.03 mA最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：CMOS
温度等级：COMMERCIAL端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
切换位：NO宽度：15.24 mm
Base Number Matches：1

SST27SF256-70-3C-PGE 数据手册

 浏览型号SST27SF256-70-3C-PGE的Datasheet PDF文件第2页浏览型号SST27SF256-70-3C-PGE的Datasheet PDF文件第3页浏览型号SST27SF256-70-3C-PGE的Datasheet PDF文件第4页浏览型号SST27SF256-70-3C-PGE的Datasheet PDF文件第5页浏览型号SST27SF256-70-3C-PGE的Datasheet PDF文件第6页浏览型号SST27SF256-70-3C-PGE的Datasheet PDF文件第7页 
256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit (x8)  
Many-Time Programmable Flash  
SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020  
SST27SF256 / 512 / 010 / 0205.0V-Read 256Kb / 512Kb / 1Mb / 2Mb (x8) MTP flash memories  
Data Sheet  
FEATURES:  
•
•
•
Organized as 32K x8 / 64K x8 / 128K x8 / 256K x8  
4.5-5.5V Read Operation  
Superior Reliability  
– Endurance: At least 1000 Cycles  
– Greater than 100 years Data Retention  
•
Fast Byte-Program Operation  
– Byte-Program Time: 20 µs (typical)  
– Chip Program Time:  
0.7 seconds (typical) for SST27SF256  
1.4 seconds (typical) for SST27SF512  
2.8 seconds (typical) for SST27SF010  
5.6 seconds (typical) for SST27SF020  
•
•
Low Power Consumption  
– Active Current: 20 mA (typical)  
– Standby Current: 10 µA (typical)  
•
Electrical Erase Using Programmer  
– Does not require UV source  
– Chip-Erase Time: 100 ms (typical)  
Fast Read Access Time  
– 70 ns  
– 90 ns  
•
•
•
TTL I/O Compatibility  
JEDEC Standard Byte-wide EPROM Pinouts  
Packages Available  
– 32-lead PLCC  
– 32-lead TSOP (8mm x 14mm)  
– 28-pin PDIP for SST27SF256/512  
– 32-pin PDIP for SST27SF010/020  
PRODUCT DESCRIPTION  
The SST27SF256/512/010/020 are a 32K x8 / 64K x8 /  
128K x8 / 256K x8 CMOS, Many-Time Programmable  
(MTP) low cost flash, manufactured with SST’s proprietary,  
high performance SuperFlash technology. The split-gate  
cell design and thick oxide tunneling injector attain better  
reliability and manufacturability compared with alternate  
approaches. These MTP devices can be electrically erased  
and programmed at least 1000 times using an external pro-  
grammer with a 12 volt power supply. They have to be  
erased prior to programming. These devices conform to  
JEDEC standard pinouts for byte-wide memories.  
Device Operation  
The SST27SF256/512/010/020 are a low cost flash  
solution that can be used to replace existing UV-  
EPROM, OTP, and mask ROM sockets. These devices  
are functionally (read and program) and pin compatible  
with industry standard EPROM products. In addition to  
EPROM functionality, these devices also support elec-  
trical Erase operation via an external programmer. They  
do not require a UV source to erase, and therefore the  
packages do not have a window.  
Featuring high performance Byte-Program, the  
SST27SF256/512/010/020 provide a Byte-Program time of  
20 µs. Designed, manufactured, and tested for a wide  
spectrum of applications, these devices are offered with an  
endurance of at least 1000 cycles. Data retention is rated at  
greater than 100 years.  
Read  
The Read operation of the SST27SF256/512/010/020 is  
controlled by CE# and OE#. Both CE# and OE# have to be  
low for the system to obtain data from the outputs. Once  
the address is stable, the address access time is equal to  
the delay from CE# to output (TCE). Data is available at the  
output after a delay of TOE from the falling edge of OE#,  
assuming that CE# pin has been low and the addresses  
have been stable for at least TCE-TOE. When the CE# pin is  
high, the chip is deselected and a typical standby current of  
10 µA is consumed. OE# is the output control and is used  
to gate data from the output pins. The data bus is in high  
impedance state when either CE# or OE# is high.  
The SST27SF256/512/010/020 are suited for applications  
that require infrequent writes and low power nonvolatile  
storage. These devices will improve flexibility, efficiency,  
and performance while matching the low cost in nonvolatile  
applications that currently use UV-EPROMs, OTPs, and  
mask ROMs.  
To meet surface mount and conventional through hole  
requirements, the SST27SF256/512 are offered in 32-lead  
PLCC, 32-lead TSOP, and 28-pin PDIP packages. The  
SST27SF010/020 are offered in 32-pin PDIP, 32-lead  
PLCC, and 32-lead TSOP packages. See Figures 1, 2, and  
3 for pin assignments.  
©2003 Silicon Storage Technology, Inc.  
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.  
MTP is a trademark of Silicon Storage Technology, Inc.  
S71152-06-000  
1
11/03  
These specifications are subject to change without notice.  
1234567...28

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