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SSM2517CBZ-R7

更新时间: 2024-11-04 02:51:47
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亚德诺 - ADI 光电二极管
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16页 429K
描述
PDM Digital Input, Mono 2.4 W Class-D Audio Amplifier

SSM2517CBZ-R7 数据手册

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PDM Digital Input, Mono  
2.4 W Class-D Audio Amplifier  
SSM2517  
enables extremely low real-world power consumption from  
digital audio sources with excellent audio performance. Using  
the SSM2517, audio can be transmitted digitally to the audio  
amplifier, significantly reducing the effect of noise sources such as  
GSM interference or other digital signals on the transmitted audio.  
The SSM2517 is capable of delivering 2.4 W of continuous output  
power with <1% THD + N driving a 4 Ω load from a 5.0 V supply.  
Data Sheet  
FEATURES  
Filterless digital Class-D amplifier  
Pulse density modulation (PDM) digital input interface  
2.4 W into 4 Ω load and 1.38 W into 8 Ω load at 5.0 V supply  
with <1% total harmonic distortion plus noise (THD + N)  
Available in 9-ball, 1.5 mm × 1.5 mm, 0.5 mm pitch WLCSP  
92% efficiency into 8 Ω at full scale  
Output noise: 43 μV rms at 3.6 V, A-weighted  
THD + N: 0.035% at 1 kHz, 100 mW output power  
PSRR: 85 dB at 217 Hz, input referred with dither input  
Quiescent power consumption: 10.4 mW  
(VDD = 1.8 V, PVDD = 3.6 V, 8 Ω + 33 μH load)  
Pop-and-click suppression  
The SSM2517 features a high efficiency, low noise modulation  
scheme that requires no external LC output filters. The closed-loop,  
three-level modulator design retains the benefits of an all-digital  
amplifier, yet enables very good PSRR and audio performance. The  
modulation continues to provide high efficiency even at low output  
power and has an SNR of 96 dB. Spread-spectrum pulse density  
modulation is used to provide lower EMI-radiated emissions  
compared with other Class-D architectures.  
Configurable with PDM pattern inputs  
Short-circuit and thermal protection with autorecovery  
Smart power-down when PDM stop condition  
or no clock input detected  
64 × fS or 128 × fS operation supporting 3 MHz and 6 MHz clocks  
DC blocking high-pass filter and static input dc protection  
User-selectable ultralow EMI emissions mode  
Power-on reset (POR)  
The SSM2517 has a four-state gain and sample frequency selection  
pin that can select two different gain settings, optimized for 3.6 V  
and 5 V operation. This same pin also controls the internal digital  
filtering and clocking, which can be set for 64 × fS or 128 × fS input  
sample rates to support both 3 MHz and 6 MHz PDM clock rates.  
The SSM2517 has a micropower shutdown mode with a typical  
shutdown current of 1 μA for both power supplies. Shutdown is  
enabled automatically by gating input clock and data signals. A  
standby mode can be entered by applying a designated PDM stop  
condition sequence. The device also includes pop-and-click sup-  
pression circuitry. This suppression circuitry minimizes voltage  
glitches at the output when entering or leaving the low power  
state, reducing audible noises on activation and deactivation.  
Minimal external passive components  
APPLICATIONS  
Mobile handsets  
GENERAL DESCRIPTION  
The SSM2517 is a PDM digital input Class-D power amplifier  
that offers higher performance than existing DAC plus Class-D  
solutions. The SSM2517 is ideal for power sensitive applications,  
such as mobile phones and portable media players, where system  
noise can corrupt the small analog signal sent to the amplifier.  
The SSM2517 is specified over the industrial temperature range  
of −40°C to +85°C. It has built-in thermal shutdown and output  
short-circuit protection. It is available in a 9-ball, 1.5 mm × 1.5 mm  
wafer level chip scale package (WLCSP).  
The SSM2517 combines an audio digital-to-analog converter  
(DAC), a power amplifier, and a PDM digital interface on a single  
chip. The integrated DAC plus analog Σ-Δ modulator architecture  
FUNCTIONAL BLOCK DIAGRAM  
VDD  
PVDD  
PGND  
SSM2517  
POWER-ON  
RESET  
CLOCKING POWER  
CONTROL  
PDAT  
PCLK  
OUT+  
OUT–  
Σ-∆  
INPUT  
INTERFACE  
FILTERING/  
DAC  
FULL-BRIDGE  
POWER STAGE  
CLASS-D  
MODULATOR  
GAIN_FS  
LRSEL  
Figure 1.  
Rev. B  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700 www.analog.com  
Fax: 781.461.3113 ©2010-2011 Analog Devices, Inc. All rights reserved.  
 

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