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SP5669KGMP1T PDF预览

SP5669KGMP1T

更新时间: 2024-11-25 22:20:03
品牌 Logo 应用领域
MITEL /
页数 文件大小 规格书
15页 240K
描述
2.7GHz I2C Bus Controlled Synthesiser

SP5669KGMP1T 数据手册

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SP5669  
2.7GHz I2C Bus Controlled Synthesiser  
Preliminary Information  
DS4852 -  
Issue 2.1  
May 1999  
Features  
Ordering Information  
Complete 2.7GHz single chip system  
Compatible with UK DTT offset requirements  
Optimised for low phase noise  
Selectable divide by two prescaler  
Selectable reference division ratio  
Selectable reference/comparison frequency output  
Selectable charge pump current  
SP5669/KG/MP1S (Tubes)  
SP5669/KG/MP1T (Tape and reel)  
Four selectable I2C bus address  
5–level ADC  
Pin compatible with the SP5658 3–wire bus  
controlled synthesiser and SP5659 I2C bus  
synthesiser and SP5659 I2C bus synthesiser  
ESD protection; (Normal ESD handling  
procedures should be observed)  
The comparison frequency is obtained either from an  
on–chip crystal controlled oscillator, or from an external  
source. The oscillator frequency Fref or the comparison  
frequency Fcomp may be switched to the REF/COMP  
output. This feature is ideally suited to providing the  
referencefrequencyforasecondsynthesisersuchasin  
a double conversion tuner (see Fig. 8).  
The synthesiser is controlled via an I 2 C bus, and  
respondstooneoffourprogrammableaddresseswhich  
are selected by applying a specific voltage to the  
‘address’ input. This feature enables two or more  
synthesisers to be used in a system.  
Applications  
Complete 2.7GHz single chip system  
Optimised for low phase noise  
The device contains four switching ports P0–P3 and a  
Description  
5–level ADC. The output of the ADC can be read via the  
I 2 C  
bus.  
The SP5669 is a single chip frequency synthesiser  
designed for tuning systems up to 2.7GHz and offers  
step size compatible with DTT offset requirements.  
The device also contains a varactor line disable and  
chargepump disable facility.  
The RF preamplifier drives a divide by two prescaler  
which can be disabled for applications up to 2GHz,  
allowing direct interfacing with the programmable  
divider so enabling a step size equal to the comparison  
frequency. For applications up to 2.7GHz the divide by  
two is enabled, giving a step size of twice the  
comparison frequency.  

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