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SP5730A/KG/QP1S

更新时间： 2024-10-31 22:06:59
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 信号电路锁相环或频率合成电路光电二极管
页数 文件大小 规格书
12页 380K
描述
1.3 GHz Low Phase Noise Frequency Synthesiser

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SP5730A/KG/QP1S 技术参数

是否Rohs认证： 不符合生命周期：Transferred
包装说明：SSOP, SSOP16,.25Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.76
Is Samacsys：N模拟集成电路 - 其他类型：PLL FREQUENCY SYNTHESIZER
JESD-30 代码：R-PDSO-G16JESD-609代码：e0
长度：4.9 mm功能数量：1
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装等效代码：SSOP16,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, SHRINK PITCH
电源：5 V认证状态：Not Qualified
座面最大高度：1.75 mm子类别：PLL or Frequency Synthesis Circuits
最大供电电流 (Isup)：20 mA最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：BIPOLAR
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.635 mm
端子位置：DUAL宽度：3.9 mm
Base Number Matches：1

SP5730A/KG/QP1S 数据手册

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SP5730  
1.3 GHz Low Phase Noise Frequency Synthesiser  
Data Sheet  
November 2004  
Features  
Ordering Information  
• Complete 1·3 GHz Single Chip System for Digital  
SP5730A/KG/QP1T 16 Pin QSOP Tape & Reel  
SP5730A/KG/QP1S 16 Pin QSOP Tubes  
SP5730A/KG/MP1S 16 Pin SOIC Tubes  
SP5730A/KG/MP2S 16 Pin SOIC* Tubes  
SP5730A/KG/QP2T 16 Pin QSOP* Tape & Reel  
SP5730A/KG/MP1T 16 Pin SOIC Tape & Reel  
SP5730A/KG/MP2T 16 Pin SOIC* Tape & Reel  
SP5730A/KG/QP2S 16 Pin QSOP* Tubes  
*Pb Free Matte Tin  
Terrestrial Television Applications  
• Selectable Reference Division Ratio, Compatible with  
DTT Requirements  
• Optimised for Low Phase Noise, with Comparison  
Frequencies up to 4 MHz  
• No RF Prescaler  
• Selectable Reference/Comparison Frequency Output  
prescaler phase noise degradation over the full RF  
operating range. The comparison frequency is obtained  
either from an on-chip crystal controlled oscillator, or from  
an external source. The oscillator frequency, fREF, or phase  
comparator frequency, fCOMP, can be switched to the REF/  
COMP output providing a reference for a second  
frequency synthesiser. The synthesiser is controlled via  
an 12C bus and is fast mode compliant. It can be hard  
wired to respond to one of four addresses to enable two  
or more synthesisers to be used on a common bus. The  
device contains four switching ports P0 - P3.  
• Four Selectable I2C Addresses  
• I2C Fast Mode Compliant with 3·3V and 5V Logic  
Levels  
• Four Switching Ports  
• Functional Replacement for SP5659 (except ADC)  
• Pin Compatible with SP5655  
• Power Consumption 120mW with VCC = 5·5V, all Ports off  
• ESD Protection 2kV min., MIL-STD-883B Method 3015  
Cat.1 (Normal ESD handling procedures should be  
observed)  
Applications  
• Digital Satellite, Cable and TerrestrialTuning Systems  
Absolute Maximum Ratings  
All voltages are referred to VEE = 0V  
• Communications Systems  
Supply voltage, VCC  
RF differential input voltage  
All I/O port DC offsets  
SDA and SCL DC offset  
Storage temperature  
Junction temperature  
QP16 thermal resistance  
Chip to ambient, θJA  
Chip to case, θJC  
-0·3V to +7V  
2·5Vp-p  
-0·3 to VCC +0·3V  
-0·3 to 6V  
-55°C to +150°C  
+150°C  
Description  
The SP5730 is a single chip frequency synthesiser  
designed for tuning systems up to 1·3GHz and is  
optimised for digital terrestrial applications. The RF  
preamplifier interfaces direct with the RF programmable  
divider, which is of MN1A construction so giving a step  
size equal to the loop comparison frequency and no  
80°C/W  
20°C/W  
11  
REF/COMP  
2
3
CRYSTAL CAP  
CRYSTAL  
12-BIT  
COUNT  
REFERENCE  
DIVIDER  
13  
RF  
INPUT  
48/9  
ENABLE/  
SELECT  
14  
3-BIT  
COUNT  
1
CHARGE PUMP  
DRIVE  
LOCK  
16  
PUMP  
f
PD  
/2  
CP MODE  
DISABLE  
2 BIT  
5 BIT  
2 BIT  
2 BIT  
15-BIT LATCH  
10  
4
ADDRESS  
SDA  
2
I C BUS  
TRANSCEIVER  
5
SCL  
f /2 SELECT  
PD  
4-BIT LATCH AND  
PORT INTERFACE  
6
7
8
9
P3 P2  
P1 P0  
Figure 1 - SP5730 block diagram  
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 2001-2004, Zarlink Semiconductor Inc. All Rights Reserved.  
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