SP5730
1.3 GHz Low Phase Noise Frequency Synthesiser
Data Sheet
November 2004
Features
Ordering Information
• Complete 1·3 GHz Single Chip System for Digital
SP5730A/KG/QP1T 16 Pin QSOP Tape & Reel
SP5730A/KG/QP1S 16 Pin QSOP Tubes
SP5730A/KG/MP1S 16 Pin SOIC Tubes
SP5730A/KG/MP2S 16 Pin SOIC* Tubes
SP5730A/KG/QP2T 16 Pin QSOP* Tape & Reel
SP5730A/KG/MP1T 16 Pin SOIC Tape & Reel
SP5730A/KG/MP2T 16 Pin SOIC* Tape & Reel
SP5730A/KG/QP2S 16 Pin QSOP* Tubes
*Pb Free Matte Tin
Terrestrial Television Applications
• Selectable Reference Division Ratio, Compatible with
DTT Requirements
• Optimised for Low Phase Noise, with Comparison
Frequencies up to 4 MHz
• No RF Prescaler
• Selectable Reference/Comparison Frequency Output
prescaler phase noise degradation over the full RF
operating range. The comparison frequency is obtained
either from an on-chip crystal controlled oscillator, or from
an external source. The oscillator frequency, fREF, or phase
comparator frequency, fCOMP, can be switched to the REF/
COMP output providing a reference for a second
frequency synthesiser. The synthesiser is controlled via
an 12C bus and is fast mode compliant. It can be hard
wired to respond to one of four addresses to enable two
or more synthesisers to be used on a common bus. The
device contains four switching ports P0 - P3.
• Four Selectable I2C Addresses
• I2C Fast Mode Compliant with 3·3V and 5V Logic
Levels
• Four Switching Ports
• Functional Replacement for SP5659 (except ADC)
• Pin Compatible with SP5655
• Power Consumption 120mW with VCC = 5·5V, all Ports off
• ESD Protection 2kV min., MIL-STD-883B Method 3015
Cat.1 (Normal ESD handling procedures should be
observed)
Applications
• Digital Satellite, Cable and TerrestrialTuning Systems
Absolute Maximum Ratings
All voltages are referred to VEE = 0V
• Communications Systems
Supply voltage, VCC
RF differential input voltage
All I/O port DC offsets
SDA and SCL DC offset
Storage temperature
Junction temperature
QP16 thermal resistance
Chip to ambient, θJA
Chip to case, θJC
-0·3V to +7V
2·5Vp-p
-0·3 to VCC +0·3V
-0·3 to 6V
-55°C to +150°C
+150°C
Description
The SP5730 is a single chip frequency synthesiser
designed for tuning systems up to 1·3GHz and is
optimised for digital terrestrial applications. The RF
preamplifier interfaces direct with the RF programmable
divider, which is of MN1A construction so giving a step
size equal to the loop comparison frequency and no
80°C/W
20°C/W
11
REF/COMP
2
3
CRYSTAL CAP
CRYSTAL
12-BIT
COUNT
REFERENCE
DIVIDER
13
RF
INPUT
48/9
ENABLE/
SELECT
14
3-BIT
COUNT
1
CHARGE PUMP
DRIVE
LOCK
16
PUMP
f
PD
/2
CP MODE
DISABLE
2 BIT
5 BIT
2 BIT
2 BIT
15-BIT LATCH
10
4
ADDRESS
SDA
2
I C BUS
TRANSCEIVER
5
SCL
f /2 SELECT
PD
4-BIT LATCH AND
PORT INTERFACE
6
7
8
9
P3 P2
P1 P0
Figure 1 - SP5730 block diagram
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2001-2004, Zarlink Semiconductor Inc. All Rights Reserved.