5秒后页面跳转
捷配首页

Datasheet > SNJ54LVC373AW
SNJ54LVC373AW PDF预览

SNJ54LVC373AW

更新时间： 2024-01-27 09:49:30
品牌 Logo 应用领域
德州仪器 - TI 锁存器输出元件
页数 文件大小 规格书
22页 757K
描述
OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

阅读下载

中文翻译

获取价格

SNJ54LVC373AW 技术参数

是否无铅： 不含铅是否Rohs认证： 不符合
生命周期：Active零件包装代码：DFP
包装说明：DFP, FL20,.3针数：16
Reach Compliance Code：not_compliantHTS代码：8542.39.00.01
Factory Lead Time：6 weeks风险等级：5.53
控制类型：ENABLE LOW计数方向：UNIDIRECTIONAL
系列：LVC/LCX/ZJESD-30 代码：R-GDFP-F16
JESD-609代码：e0长度：10.16 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS DRIVER
最大I（ol）：0.024 A位数：8
功能数量：1端口数量：2
端子数量：16最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DFP封装等效代码：FL20,.3
封装形状：RECTANGULAR封装形式：FLATPACK
包装方法：TUBE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 V最大电源电流（ICC）：0.01 mA
Prop。Delay @ Nom-Sup：7.5 ns传播延迟（tpd）：9.5 ns
认证状态：Not Qualified筛选级别：MIL-PRF-38535
座面最大高度：2.45 mm子类别：FF/Latches
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：2.7 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子面层：Tin/Lead (Sn/Pb)端子形式：FLAT
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：6.92 mm

SNJ54LVC373AW 数据手册

 浏览型号SNJ54LVC373AW的Datasheet PDF文件第2页浏览型号SNJ54LVC373AW的Datasheet PDF文件第3页浏览型号SNJ54LVC373AW的Datasheet PDF文件第4页浏览型号SNJ54LVC373AW的Datasheet PDF文件第5页浏览型号SNJ54LVC373AW的Datasheet PDF文件第6页浏览型号SNJ54LVC373AW的Datasheet PDF文件第7页 
SN54LVC373A, SN74LVC373A  
OCTAL TRANSPARENT D-TYPE LATCHES  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCAS295S–JANUARY 1993–REVISED MAY 2005  
FEATURES  
•
•
•
Ioff Supports Partial-Power-Down Mode  
Operation  
•
•
•
•
Operate From 1.65 V to 3.6 V  
Inputs Accept Voltages to 5.5 V  
Max tpd of 6.8 ns at 3.3 V  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
Typical VOLP (Output Ground Bounce) < 0.8 V  
at VCC = 3.3 V, TA = 25°C  
•
•
Typical VOHV (Output VOH Undershoot) > 2 V at  
VCC = 3.3 V, TA = 25°C  
– 1000-V Charged-Device Model (C101)  
ABC  
Support Mixed-Mode Signal Operation on All  
Ports (5-V Input/Output Voltage With  
3.3-V VCC  
)
SN54LVC373A . . . J OR W PACKAGE  
SN74LVC373A . . . DB, DGV, DW, N,  
NS, OR PW PACKAGE  
SN74LVC373A . . . RGY PACKAGE  
(TOP VIEW)  
SN54LVC373A . . . FK PACKAGE  
(TOP VIEW)  
(TOP VIEW)  
1
20  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
OE  
1Q  
1D  
V
CC  
3
9
2
1
20 19  
18  
2D  
2Q  
3Q  
3D  
4D  
8D  
7D  
7Q  
6Q  
6D  
2
3
4
5
6
7
8
9
19  
18  
17  
16  
15  
14  
13  
12  
4
5
6
7
8
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
8Q  
8D  
7D  
7Q  
6Q  
6D  
5D  
5Q  
8Q  
8D  
7D  
7Q  
6Q  
6D  
5D  
5Q  
LE  
17  
16  
15  
14  
2D  
2Q  
3Q  
10 11 12 13  
3D  
4D  
4Q  
GND  
10  
11  
DESCRIPTION/ORDERING INFORMATION  
The SN54LVC373A octal transparent D-type latch is designed for 2.7-V to 3.6-V VCC operation, and the  
SN74LVC373A octal transparent D-type latch is designed for 1.65-V to 3.6-V VCC operation.  
While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q  
outputs are latched at the logic levels set up at the D inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or  
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the  
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines  
without interface or pullup components.  
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the  
outputs, preventing damaging current backflow through the devices when they are powered down.  
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators  
in a mixed 3.3-V/5-V system environment.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1993–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
On products compliant to MIL-PRF-38535, all parameters are  
Instruments standard warranty. Production processing does not  
tested unless otherwise noted. On all other products, production  
necessarily include testing of all parameters.  
processing does not necessarily include testing of all parameters.  
1234567...22

中文翻译

下载PDF

SNJ54LVC373AW 替代型号

型号 品牌 替代类型 描述 数据表
5962-9757301QSA TI

完全替代

 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN54LVC373AW TI

功能相似

 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

与SNJ54LVC373AW相关器件

型号 品牌 获取价格 描述 数据表
SNJ54LVC374AFK TI

获取价格

 		OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SNJ54LVC374AFKR TI

获取价格

 		LVC/LCX/Z SERIES, 8-BIT DRIVER, TRUE OUTPUT, CQCC20, CERAMIC, LCC-20
SNJ54LVC374AJ TI

获取价格

 		OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SNJ54LVC374AW TI

获取价格

 		OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SNJ54LVC374AWR TI

获取价格

 		LVC/LCX/Z SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDFP20, CERAMIC, DFP-20
SNJ54LVC540AFK TI

获取价格

 		OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SNJ54LVC540AJ TI

获取价格

 		OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SNJ54LVC540AW TI

获取价格

 		OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SNJ54LVC541AFK TI

获取价格

 		OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUT
SNJ54LVC541AFKR TI

获取价格

 		LVC/LCX/Z SERIES, 8-BIT DRIVER, TRUE OUTPUT, CQCC20, HERMETIC SEALED, CERAMIC, LCC-20

与SNJ54LVC373AW相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证