5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 总线驱动器/收发器> SNJ54LVC574AJ
SNJ54LVC574AJ PDF预览

SNJ54LVC574AJ

更新时间： 2024-11-23 05:16:51
品牌 Logo 应用领域
德州仪器 - TI 触发器输出元件
页数 文件大小 规格书
25页 915K
描述
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

阅读下载

中文翻译

获取价格

SNJ54LVC574AJ 技术参数

是否无铅： 不含铅是否Rohs认证： 不符合
生命周期：Active零件包装代码：DIP
包装说明：DIP, DIP20,.3针数：16
Reach Compliance Code：not_compliantHTS代码：8542.39.00.01
Factory Lead Time：16 weeks风险等级：5.48
控制类型：ENABLE LOW计数方向：UNIDIRECTIONAL
系列：LVC/LCX/ZJESD-30 代码：R-GDIP-T16
JESD-609代码：e0长度：24.195 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS DRIVER
最大频率@ Nom-Sup：150000000 Hz最大I（ol）：0.024 A
位数：8功能数量：1
端口数量：2端子数量：16
最高工作温度：125 °C最低工作温度：-55 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DIP
封装等效代码：DIP20,.3封装形状：RECTANGULAR
封装形式：IN-LINE包装方法：TUBE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3.3 V
最大电源电流（ICC）：0.01 mAProp。Delay @ Nom-Sup：7 ns
传播延迟（tpd）：8 ns认证状态：Not Qualified
筛选级别：MIL-PRF-38535座面最大高度：5.08 mm
子类别：FF/Latches最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：2.7 V
表面贴装：NO技术：CMOS
温度等级：MILITARY端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
触发器类型：POSITIVE EDGE宽度：7.62 mm

SNJ54LVC574AJ 数据手册

 浏览型号SNJ54LVC574AJ的Datasheet PDF文件第2页浏览型号SNJ54LVC574AJ的Datasheet PDF文件第3页浏览型号SNJ54LVC574AJ的Datasheet PDF文件第4页浏览型号SNJ54LVC574AJ的Datasheet PDF文件第5页浏览型号SNJ54LVC574AJ的Datasheet PDF文件第6页浏览型号SNJ54LVC574AJ的Datasheet PDF文件第7页 
ꢀꢁꢂ ꢃ ꢄꢅꢆꢂ ꢇ ꢃ ꢈꢉ ꢀꢁꢇ ꢃꢄꢅ ꢆꢂ ꢇꢃ ꢈ  
ꢊ ꢆꢋꢈꢄ ꢌꢍ ꢎꢌ ꢏꢋꢐ ꢑꢎ ꢎꢌ ꢐꢌꢍ ꢍꢏꢋ ꢒꢓ ꢌ ꢔ ꢄꢑ ꢓ ꢏꢔ ꢄꢊ ꢓꢀ  
ꢕ ꢑꢋ ꢖ ꢗ ꢏꢀꢋꢈꢋ ꢌ ꢊ ꢘꢋ ꢓ ꢘꢋꢀ  
SCAS301R − JANUARY 1993 − REVISED MARCH 2005  
D
D
D
Operate From 1.65 V to 3.6 V  
Inputs Accept Voltages to 5.5 V  
D
Support Mixed-Mode Signal Operation on  
All Ports (5-V Input/Output Voltage With  
3.3-V V  
)
CC  
Specified From −40°C to 85°C,  
−40°C to 125°C, and −55°C to 125°C  
Max t of 7 ns at 3.3 V  
pd  
D
D
D
I
Supports Partial-Power-Down Mode  
off  
Operation  
D
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
D
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
= 3.3 V, T = 25°C  
A
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
D
Typical V  
(Output V  
Undershoot)  
OHV  
OH  
>2 V at V  
= 3.3 V, T = 25°C  
CC  
A
− 1000-V Charged-Device Model (C101)  
SN54LVC574A . . . FK PACKAGE  
SN54LVC574A . . . J OR W PACKAGE  
SN74LVC574A . . . DB, DGV, DW, N, NS,  
OR PW PACKAGE  
SN74LVC574A . . . RGY PACKAGE  
(TOP VIEW)  
(TOP VIEW)  
(TOP VIEW)  
1
20  
3
2 1 20 19  
18  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
1Q  
1
2
3
4
5
6
7
8
9
10  
20  
19  
2Q  
3Q  
4Q  
5Q  
6Q  
3D  
4D  
5D  
6D  
7D  
4
5
6
7
8
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
1Q  
2
3
4
5
6
7
8
9
19  
17  
16  
15  
14  
18 2Q  
18 2Q  
17 3Q  
16 4Q  
17  
16  
15  
14  
13  
12  
3Q  
4Q  
5Q  
6Q  
7Q  
8Q  
15  
14  
13  
12  
11  
5Q  
6Q  
7Q  
8Q  
CLK  
9 10 11 12 13  
10  
11  
GND  
description/ordering information  
The SN54LVC574A octal edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V V  
operation, and the  
operation.  
CC  
SN74LVC574A octal edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V V  
CC  
These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively  
low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional  
bus drivers, and working registers.  
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels at the data (D) inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive  
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus  
lines without interface or pullup components.  
OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
These devices are fully specified for partial-power-down applications using I . The I circuitry disables the  
off  
off  
outputs, preventing damaging current backflow through the device when it is powered down.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢓ
ꢓ
ꢐ
ꢊ
ꢨ
ꢍ
ꢣ
ꢟ
ꢘ
ꢆ
ꢡ
ꢋ
ꢢ
ꢬ
ꢑ
ꢜ
ꢊ
ꢚ
ꢝ
ꢁ
ꢛ
ꢍ
ꢈ
ꢋ
ꢈ
ꢙ
ꢚ
ꢤ
ꢣ
ꢛ
ꢜ
ꢢ
ꢢ
ꢝ
ꢞ
ꢟ
ꢟ
ꢚ
ꢠ
ꢠ
ꢙ
ꢙ
ꢥ
ꢜ
ꢜ
ꢝ
ꢚ
ꢚ
ꢜ
ꢙ
ꢡ
ꢡ
ꢥ
ꢡ
ꢢ
ꢣ
ꢝ
ꢝ
ꢤ
ꢤ
ꢚ
ꢠ
ꢟ
ꢞ
ꢡ
ꢡ
ꢡ
ꢚ
ꢜ
ꢛ
ꢥ
ꢣ
ꢦ
ꢡ
ꢡ
ꢧ
ꢙ
ꢢ
ꢟ
ꢡ
ꢠ
ꢙ
ꢠ
ꢭ
ꢜ
ꢝ
ꢚ
ꢣ
ꢨ
ꢟ
ꢚ
ꢨ
ꢠ
ꢠ
ꢤ
ꢡ
ꢤ
ꢩ
Copyright 2005, Texas Instruments Incorporated  
ꢊ ꢚ ꢥ ꢝ ꢜꢨ ꢣꢢ ꢠꢡ ꢢꢜ ꢞꢥ ꢧꢙ ꢟꢚ ꢠ ꢠꢜ ꢯꢑ ꢄꢏ ꢓꢐ ꢔ ꢏꢗꢰꢂ ꢗꢂꢉ ꢟꢧꢧ ꢥꢟ ꢝ ꢟ ꢞꢤ ꢠꢤꢝ ꢡ ꢟ ꢝ ꢤ ꢠꢤ ꢡꢠꢤ ꢨ  
ꢝ
ꢜ
ꢢ
ꢠ
ꢜ
ꢝ
ꢞ
ꢠ
ꢜ
ꢡ
ꢥ
ꢙ
ꢛ
ꢙ
ꢢ
ꢤ
ꢝ
ꢠ
ꢪ
ꢠ
ꢤ
ꢝ
ꢜ
ꢛ
ꢋ
ꢤ
ꢫ
ꢟ
ꢑ
ꢚ
ꢞ
ꢤ
ꢡ
ꢠ
ꢟ
ꢚ
ꢨ
ꢝ
ꢨ
ꢟ
ꢠ ꢤ ꢡ ꢠꢙ ꢚꢮ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢩ  
ꢝ
ꢟ
ꢚ
ꢠꢭ  
ꢩ
ꢓ
ꢝ
ꢜ
ꢨ
ꢠ
ꢙ
ꢜ
ꢢ
ꢤ
ꢡ
ꢙ
ꢚ
ꢮ
ꢨ
ꢜ
ꢤ
ꢜ
ꢠ
ꢚ
ꢤ
ꢢ
ꢤ
ꢡ
ꢟ
ꢝ
ꢙ
ꢧ
ꢙ
ꢚ
ꢢ
ꢧ
ꢣ
ꢣ ꢚꢧ ꢤꢡꢡ ꢜ ꢠꢪꢤ ꢝ ꢬꢙ ꢡꢤ ꢚ ꢜꢠꢤ ꢨꢩ ꢊ ꢚ ꢟꢧ ꢧ ꢜ ꢠꢪꢤ ꢝ ꢥꢝ ꢜ ꢨꢣꢢ ꢠꢡ ꢉ ꢥꢝ ꢜ ꢨꢣꢢ ꢠꢙꢜ ꢚ  
ꢠ
ꢥ
ꢝ
ꢜ
ꢢ
ꢤ
ꢡ
ꢡ
ꢙ
ꢚ
ꢮ
ꢨ
ꢜ
ꢤ
ꢡ
ꢚ
ꢜ
ꢠ
ꢚ
ꢤ
ꢢ
ꢤ
ꢡ
ꢡ
ꢟ
ꢝ
ꢙ
ꢧ
ꢭ
ꢙ
ꢚ
ꢢ
ꢧ
ꢣ
ꢨ
ꢤ
ꢠ
ꢤ
ꢡ
ꢙ
ꢚ
ꢮ
ꢜ
ꢛ
ꢟ
ꢧ
ꢧ
ꢥ
ꢟ
ꢝ
ꢟ
ꢞ
ꢤ
ꢠ
ꢤ
ꢝ
ꢡ
ꢩ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...25

中文翻译

下载PDF

与SNJ54LVC574AJ相关器件

型号 品牌 获取价格 描述 数据表
SNJ54LVC574AW TI

获取价格

 		OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SNJ54LVC652AFK TI

获取价格

 		OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS 28-LCCC -55 to 125
SNJ54LVC74AFK TI

获取价格

 		DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SNJ54LVC74AJ TI

获取价格

 		DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SNJ54LVC74AW TI

获取价格

 		DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SNJ54LVC86AFK TI

获取价格

 		QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SNJ54LVC86AJ TI

获取价格

 		QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SNJ54LVC86AW TI

获取价格

 		QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SNJ54LVCH244AFK TI

获取价格

 		OCTAL BUFFERS/DRIVERS OCTAL BUFFERS/DRIVERS
SNJ54LVCH244AJ TI

获取价格

 		OCTAL BUFFERS/DRIVERS OCTAL BUFFERS/DRIVERS

与SNJ54LVC574AJ相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证