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SNJ54LVC574AFK PDF预览

SNJ54LVC574AFK

更新时间: 2024-11-23 05:16:51
品牌 Logo 应用领域
德州仪器 - TI 触发器输出元件
页数 文件大小 规格书
25页 915K
描述
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

SNJ54LVC574AFK 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QLCC
包装说明:QCCN, LCC20,.35SQ针数:20
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.87系列:LVC/LCX/Z
JESD-30 代码:S-CQCC-N20长度:8.89 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大频率@ Nom-Sup:150000000 Hz最大I(ol):0.024 A
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:QCCN
封装等效代码:LCC20,.35SQ封装形状:SQUARE
封装形式:CHIP CARRIER包装方法:TUBE
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
Prop。Delay @ Nom-Sup:7 ns传播延迟(tpd):8 ns
认证状态:Not Qualified筛选级别:MIL-PRF-38535
座面最大高度:2.03 mm子类别:FF/Latches
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):2.7 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:NO LEAD端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:8.89 mm

SNJ54LVC574AFK 数据手册

 浏览型号SNJ54LVC574AFK的Datasheet PDF文件第2页浏览型号SNJ54LVC574AFK的Datasheet PDF文件第3页浏览型号SNJ54LVC574AFK的Datasheet PDF文件第4页浏览型号SNJ54LVC574AFK的Datasheet PDF文件第5页浏览型号SNJ54LVC574AFK的Datasheet PDF文件第6页浏览型号SNJ54LVC574AFK的Datasheet PDF文件第7页 
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SCAS301R − JANUARY 1993 − REVISED MARCH 2005  
D
D
D
Operate From 1.65 V to 3.6 V  
Inputs Accept Voltages to 5.5 V  
D
Support Mixed-Mode Signal Operation on  
All Ports (5-V Input/Output Voltage With  
3.3-V V  
)
CC  
Specified From −40°C to 85°C,  
−40°C to 125°C, and −55°C to 125°C  
Max t of 7 ns at 3.3 V  
pd  
D
D
D
I
Supports Partial-Power-Down Mode  
off  
Operation  
D
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
D
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
= 3.3 V, T = 25°C  
A
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
D
Typical V  
(Output V  
Undershoot)  
OHV  
OH  
>2 V at V  
= 3.3 V, T = 25°C  
CC  
A
− 1000-V Charged-Device Model (C101)  
SN54LVC574A . . . FK PACKAGE  
SN54LVC574A . . . J OR W PACKAGE  
SN74LVC574A . . . DB, DGV, DW, N, NS,  
OR PW PACKAGE  
SN74LVC574A . . . RGY PACKAGE  
(TOP VIEW)  
(TOP VIEW)  
(TOP VIEW)  
1
20  
3
2 1 20 19  
18  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
1Q  
1
2
3
4
5
6
7
8
9
10  
20  
19  
2Q  
3Q  
4Q  
5Q  
6Q  
3D  
4D  
5D  
6D  
7D  
4
5
6
7
8
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
1Q  
2
3
4
5
6
7
8
9
19  
17  
16  
15  
14  
18 2Q  
18 2Q  
17 3Q  
16 4Q  
17  
16  
15  
14  
13  
12  
3Q  
4Q  
5Q  
6Q  
7Q  
8Q  
15  
14  
13  
12  
11  
5Q  
6Q  
7Q  
8Q  
CLK  
9 10 11 12 13  
10  
11  
GND  
description/ordering information  
The SN54LVC574A octal edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V V  
operation, and the  
operation.  
CC  
SN74LVC574A octal edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V V  
CC  
These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively  
low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional  
bus drivers, and working registers.  
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels at the data (D) inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive  
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus  
lines without interface or pullup components.  
OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
These devices are fully specified for partial-power-down applications using I . The I circuitry disables the  
off  
off  
outputs, preventing damaging current backflow through the device when it is powered down.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2005, Texas Instruments Incorporated  
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ꢠꢭ  
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1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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