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SN75ALS161_08

更新时间： 2024-11-20 04:31:15
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德州仪器 - TI 总线收发器
页数 文件大小 规格书
19页 533K
描述
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS

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SN75ALS161_08 数据手册

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ꢈ ꢉꢊꢄꢅ ꢋ ꢌꢁꢌ ꢍꢄꢅ ꢎꢏꢐꢍꢏ ꢈ ꢀꢌ ꢑꢁ ꢊꢌ ꢍꢒꢄꢉꢌ ꢓꢐꢀ ꢊ ꢍꢄꢁꢀꢉ ꢌ ꢑꢔ ꢌ ꢍꢀ  
SLLS019F − JUNE 1986 − REVISED JULY 2004  
DW OR N PACKAGE  
(TOP VIEW)  
D
D
D
Suitable for IEEE Standard 488-1978 (GPIB)  
8-Channel Bidirectional Transceivers  
TE  
V
CC  
REN  
Designed to Implement Control Bus  
Interface  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
REN  
IFC  
IFC  
D
Designed for Single Controller  
NDAC  
NRFD  
DAV  
NDAC  
NRFD  
D
High-Speed Advanced Low-Power Schottky  
Circuitry  
GPIB  
I/O Ports  
Terminal  
I/O Ports  
15 DAV  
D
Low Power Dissipation . . . 46 mW Max Per  
Channel  
14  
13  
12  
11  
EOI  
EOI  
ATN  
SRQ  
DC  
ATN  
D
D
D
D
D
D
Fast Propagation Times . . . 20 ns Max  
High-Impedance pnp Inputs  
SRQ  
GND  
Receiver Hysteresis . . . 650 mV Typ  
CHANNEL-IDENTIFICATION TABLE  
Bus-Terminating Resistors Provided on  
Driver Outputs  
NAME  
IDENTITY  
CLASS  
Control  
DC  
TE  
Direction Control  
Talk Enable  
No Loading of Bus When Device Is  
Powered Down (V  
= 0)  
CC  
ATN  
SRQ  
REN  
IFC  
Attention  
Power-Up/Power-Down Protection  
(Glitch Free)  
Service Request  
Remote Enable  
Interface Clear  
End or Identify  
Data Valid  
Bus  
Management  
description/ordering information  
EOI  
DAV  
NDAC  
NRFD  
The  
general-purpose interface bus transceivers are  
high-speed, advanced low-power  
Schottky-process devices designed to provide the  
SN75ALS161  
eight-channel  
Data  
Not Data Accepted  
Not Ready for Data  
Transfer  
bus-management and data-transfer signals between operating units of a single-controller instrumentation  
system. When combined with the SN75ALS160 octal bus transceivers, this device provides a complete 16-wire  
interface for the IEEE 488 bus.  
The SN75ALS161 device features eight driver-receiver pairs connected in a front-to-back configuration to form  
input/output (I/O) ports at both the bus and terminal sides. The direction of data through these driver-receiver  
pairs is determined by the direction-control (DC) and talk-enable (TE) signals.  
The driver outputs general-purpose interface bus (GPIB I/O ports) feature active bus-terminating resistor  
circuits designed to provide a high impedance to the bus when V  
= 0. The drivers are designed to handle  
CC  
sink-current loads up to 48 mA. Each receiver features pnp transistor inputs for high input impedance and  
hysteresis of 400 mV on the commercial part, and 250 mV on the military part, minimum, for increased noise  
immunity. All receivers have 3-state outputs, to present a high impedance to the terminal when disabled.  
The SN75ALS161 is characterized for operation from 0°C to 70°C.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP (N)  
Tube of 20  
Tube of 25  
SN75ALS161N  
SN75ALS161N  
SN75ALS161DW  
0°C to 70°C  
SOIC (DW)  
75ALS161  
Reel of 2000 SN75ALS161DWR  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
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Copyright 2004, Texas Instruments Incorporated  
ꢏꢚ ꢙ ꢥꢠꢟ ꢝ ꢞ ꢟ ꢙꢗ ꢘꢙ ꢚ ꢛ ꢝ ꢙ ꢞ ꢢꢡ ꢟ ꢖꢘ ꢖꢟꢜ ꢝꢖ ꢙꢗꢞ ꢢꢡ ꢚ ꢝꢧ ꢡ ꢝꢡ ꢚ ꢛꢞ ꢙꢘ ꢊꢡꢨ ꢜꢞ ꢑꢗꢞ ꢝꢚ ꢠꢛ ꢡꢗꢝ ꢞ  
ꢞ ꢝ ꢜ ꢗꢥ ꢜ ꢚꢥ ꢩ ꢜ ꢚꢚ ꢜ ꢗ ꢝꢪꢦ ꢏꢚ ꢙ ꢥꢠꢟ ꢝꢖꢙꢗ ꢢꢚ ꢙꢟ ꢡꢞ ꢞꢖ ꢗꢫ ꢥꢙꢡ ꢞ ꢗꢙꢝ ꢗꢡ ꢟꢡ ꢞꢞ ꢜꢚ ꢖꢤ ꢪ ꢖꢗꢟ ꢤꢠꢥ ꢡ  
ꢝ ꢡ ꢞ ꢝꢖ ꢗꢫ ꢙꢘ ꢜ ꢤꢤ ꢢꢜ ꢚ ꢜ ꢛ ꢡ ꢝ ꢡ ꢚ ꢞ ꢦ  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...19

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 		LINE TRANSCEIVER, PDIP20
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