ꢀꢁꢂ ꢃꢄ ꢅꢀ ꢆꢇ ꢆ
ꢈ ꢉꢊꢄꢅ ꢋ ꢌꢁꢌ ꢍꢄꢅ ꢎꢏꢐꢍꢏ ꢈ ꢀꢌ ꢑꢁ ꢊꢌ ꢍꢒꢄꢉꢌ ꢓꢐꢀ ꢊ ꢍꢄꢁꢀꢉ ꢌ ꢑꢔ ꢌ ꢍꢀ
SLLS019F − JUNE 1986 − REVISED JULY 2004
DW OR N PACKAGE
(TOP VIEW)
D
D
D
Suitable for IEEE Standard 488-1978 (GPIB)
8-Channel Bidirectional Transceivers
TE
V
CC
REN
Designed to Implement Control Bus
Interface
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
REN
IFC
IFC
D
Designed for Single Controller
NDAC
NRFD
DAV
NDAC
NRFD
D
High-Speed Advanced Low-Power Schottky
Circuitry
GPIB
I/O Ports
Terminal
I/O Ports
15 DAV
D
Low Power Dissipation . . . 46 mW Max Per
Channel
14
13
12
11
EOI
EOI
ATN
SRQ
DC
ATN
D
D
D
D
D
D
Fast Propagation Times . . . 20 ns Max
High-Impedance pnp Inputs
SRQ
GND
Receiver Hysteresis . . . 650 mV Typ
CHANNEL-IDENTIFICATION TABLE
Bus-Terminating Resistors Provided on
Driver Outputs
NAME
IDENTITY
CLASS
Control
DC
TE
Direction Control
Talk Enable
No Loading of Bus When Device Is
Powered Down (V
= 0)
CC
ATN
SRQ
REN
IFC
Attention
Power-Up/Power-Down Protection
(Glitch Free)
Service Request
Remote Enable
Interface Clear
End or Identify
Data Valid
Bus
Management
description/ordering information
EOI
DAV
NDAC
NRFD
The
general-purpose interface bus transceivers are
high-speed, advanced low-power
Schottky-process devices designed to provide the
SN75ALS161
eight-channel
Data
Not Data Accepted
Not Ready for Data
Transfer
bus-management and data-transfer signals between operating units of a single-controller instrumentation
system. When combined with the SN75ALS160 octal bus transceivers, this device provides a complete 16-wire
interface for the IEEE 488 bus.
The SN75ALS161 device features eight driver-receiver pairs connected in a front-to-back configuration to form
input/output (I/O) ports at both the bus and terminal sides. The direction of data through these driver-receiver
pairs is determined by the direction-control (DC) and talk-enable (TE) signals.
The driver outputs general-purpose interface bus (GPIB I/O ports) feature active bus-terminating resistor
circuits designed to provide a high impedance to the bus when V
= 0. The drivers are designed to handle
CC
sink-current loads up to 48 mA. Each receiver features pnp transistor inputs for high input impedance and
hysteresis of 400 mV on the commercial part, and 250 mV on the military part, minimum, for increased noise
immunity. All receivers have 3-state outputs, to present a high impedance to the terminal when disabled.
The SN75ALS161 is characterized for operation from 0°C to 70°C.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP (N)
Tube of 20
Tube of 25
SN75ALS161N
SN75ALS161N
SN75ALS161DW
0°C to 70°C
SOIC (DW)
75ALS161
Reel of 2000 SN75ALS161DWR
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
ꢏ
ꢏ
ꢍ
ꢈ
ꢥ
ꢕ
ꢠ
ꢐ
ꢉ
ꢞ
ꢊ
ꢟ
ꢑ
ꢙ
ꢈ
ꢗ
ꢁ
ꢘ
ꢕ
ꢄ
ꢊ
ꢄ
ꢖ
ꢗ
ꢡ
ꢘ
ꢙ
ꢟ
ꢚ
ꢛ
ꢜ
ꢜ
ꢝ
ꢝ
ꢖ
ꢖ
ꢙ
ꢙ
ꢗ
ꢗ
ꢖ
ꢞ
ꢞ
ꢢ
ꢟ
ꢠ
ꢚ
ꢚ
ꢡ
ꢡ
ꢗ
ꢝ
ꢜ
ꢛ
ꢞ
ꢞ
ꢙ
ꢘ
ꢢ
ꢊꢡ
ꢠ
ꢣ
ꢞ
ꢤ
ꢖ
ꢟ
ꢜ
ꢞ
ꢝ
ꢖ
ꢝ
ꢙ
ꢚ
ꢗ
ꢠ
ꢥ
ꢜ
ꢗ
ꢝ
ꢝ
ꢡ
ꢞ
ꢦ
Copyright 2004, Texas Instruments Incorporated
ꢚ
ꢙ
ꢟ
ꢝ
ꢙ
ꢚ
ꢛ
ꢝ
ꢙ
ꢞ
ꢢ
ꢖ
ꢘ
ꢖ
ꢟ
ꢡ
ꢚ
ꢝ
ꢧ
ꢝ
ꢡ
ꢚ
ꢙ
ꢘ
ꢨ
ꢜ
ꢑ
ꢗ
ꢛ
ꢡ
ꢞ
ꢝ
ꢜ
ꢗ
ꢥ
ꢜ
ꢚ
ꢥ
ꢩ
ꢜ
ꢝ ꢡ ꢞ ꢝꢖ ꢗꢫ ꢙꢘ ꢜ ꢤꢤ ꢢꢜ ꢚ ꢜ ꢛ ꢡ ꢝ ꢡ ꢚ ꢞ ꢦ
ꢚ
ꢚ
ꢜ
ꢗ
ꢝ
ꢪ
ꢦ
ꢏ
ꢚ
ꢙ
ꢥ
ꢠ
ꢟ
ꢝ
ꢖ
ꢙ
ꢗ
ꢢ
ꢚ
ꢙ
ꢟ
ꢡ
ꢞ
ꢞ
ꢖ
ꢗ
ꢫ
ꢥ
ꢙ
ꢡ
ꢞ
ꢗ
ꢙ
ꢝ
ꢗ
ꢡ
ꢟ
ꢡ
ꢞ
ꢞ
ꢜ
ꢚ
ꢖ
ꢤ
ꢪ
ꢖ
ꢗ
ꢟ
ꢤ
ꢠ
ꢥ
ꢡ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265