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SN74LVTH32373GKER PDF预览

SN74LVTH32373GKER

更新时间: 2024-11-18 09:12:31
品牌 Logo 应用领域
德州仪器 - TI 锁存器输出元件
页数 文件大小 规格书
11页 282K
描述
3.3-V ABT 32-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

SN74LVTH32373GKER 技术参数

生命周期:Lifetime Buy零件包装代码:BGA
包装说明:LFBGA, BGA96,6X16,32针数:96
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:7.33控制类型:ENABLE LOW/HIGH
计数方向:UNIDIRECTIONAL系列:LVT
JESD-30 代码:R-PBGA-B96JESD-609代码:e0
长度:13.5 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.064 A
湿度敏感等级:2位数:8
功能数量:4端口数量:2
端子数量:96最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:LFBGA封装等效代码:BGA96,6X16,32
封装形状:RECTANGULAR封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH
包装方法:TR峰值回流温度(摄氏度):235
电源:3.3 V最大电源电流(ICC):10 mA
Prop。Delay @ Nom-Sup:3.8 ns传播延迟(tpd):4.8 ns
认证状态:Not Qualified座面最大高度:1.4 mm
子类别:FF/Latches最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:BICMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:BALL端子节距:0.8 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
翻译:N/A宽度:5.5 mm
Base Number Matches:1

SN74LVTH32373GKER 数据手册

 浏览型号SN74LVTH32373GKER的Datasheet PDF文件第2页浏览型号SN74LVTH32373GKER的Datasheet PDF文件第3页浏览型号SN74LVTH32373GKER的Datasheet PDF文件第4页浏览型号SN74LVTH32373GKER的Datasheet PDF文件第5页浏览型号SN74LVTH32373GKER的Datasheet PDF文件第6页浏览型号SN74LVTH32373GKER的Datasheet PDF文件第7页 
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢈꢂ ꢈ  
ꢕ ꢎꢆ ꢇ ꢈ ꢋꢀꢆꢌꢆ ꢑ ꢖ ꢗꢆ ꢐ ꢗꢆꢀ  
SCBS751A − OCTOBER 2000 − REVISED SEPTEMBER 2003  
D
D
Member of the Texas Instruments  
Widebus+Family  
State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V  
Operation and Low Static-Power  
Dissipation  
D
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
D
D
D
Supports Unregulated Battery Operation  
Down to 2.7 V  
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
D
D
D
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
= 3.3 V, T = 25°C  
A
OLP  
CC  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
I
and Power-Up 3-State Support Hot  
off  
Insertion  
− 1000-V Charged-Device Model (C101)  
Supports Mixed-Mode Signal Operation  
(5-V Input and Output Voltages With  
3.3-V V  
)
CC  
GKE OR ZKE PACKAGE  
(TOP VIEW)  
terminal assignments  
1
2
3
4
5
6
1
2
3
4
5
6
A
B
C
D
E
F
1Q2  
1Q4  
1Q6  
1Q8  
2Q2  
2Q4  
2Q6  
2Q7  
3Q2  
3Q4  
3Q6  
3Q8  
4Q2  
4Q4  
4Q6  
4Q7  
1Q1  
1Q3  
1Q5  
1Q7  
2Q1  
2Q3  
2Q5  
2Q8  
3Q1  
3Q3  
3Q5  
3Q7  
4Q1  
4Q3  
4Q5  
4Q8  
1OE  
GND  
1LE  
GND  
1D1  
1D3  
1D5  
1D7  
2D1  
2D3  
2D5  
2D8  
3D1  
3D3  
3D5  
3D7  
4D1  
4D3  
4D5  
4D8  
1D2  
1D4  
1D6  
1D8  
2D2  
2D4  
2D6  
2D7  
3D2  
3D4  
3D6  
3D8  
4D2  
4D4  
4D6  
4D7  
A
B
C
D
E
F
1V  
CC  
1V  
CC  
GND  
GND  
GND  
GND  
1V  
CC  
1V  
CC  
G
H
J
GND  
2OE  
3OE  
GND  
GND  
2LE  
G
H
J
3LE  
K
L
GND  
K
L
2V  
CC  
2V  
CC  
M
N
P
R
T
GND  
GND  
GND  
GND  
M
N
P
R
T
2V  
CC  
2V  
CC  
GND  
4OE  
GND  
4LE  
description/ordering information  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
LFBGA − GKE  
LFBGA − ZKE (Pb-free)  
SN74LVTH32373GKER  
SN74LVTH32373ZKER  
−40°C to 85°C  
Tape and reel  
HV373  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus+ is a trademark of Texas Instruments.  
ꢆꢣ  
Copyright 2003, Texas Instruments Incorporated  
ꢟ ꢣ ꢠ ꢟꢘ ꢙꢬ ꢛꢚ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟ ꢣ ꢜ ꢠ ꢊ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74LVTH32373GKER 替代型号

型号 品牌 替代类型 描述 数据表
CLVTH32373IGKEREP TI

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3.3-V ABT 32-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
SN74LVTH32373ZKER TI

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