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SN74LVTH373NSR PDF预览

SN74LVTH373NSR

更新时间： 2024-10-02 05:24:47
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器锁存器逻辑集成电路光电二极管输出元件信息通信管理
页数 文件大小 规格书
19页 472K
描述
3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

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SN74LVTH373NSR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：SOP, SOP20,.3针数：20
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：1.17控制类型：ENABLE LOW
计数方向：UNIDIRECTIONAL系列：LVT
JESD-30 代码：R-PDSO-G20JESD-609代码：e4
长度：12.6 mm负载电容（CL）：50 pF
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.064 A
湿度敏感等级：1位数：8
功能数量：1端口数量：2
端子数量：20最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP20,.3
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
包装方法：TR峰值回流温度（摄氏度）：260
电源：3.3 V最大电源电流（ICC）：5 mA
Prop。Delay @ Nom-Sup：3.9 ns传播延迟（tpd）：4.9 ns
认证状态：Not Qualified座面最大高度：2 mm
子类别：FF/Latches最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：BICMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：5.3 mmBase Number Matches：1

SN74LVTH373NSR 数据手册

 浏览型号SN74LVTH373NSR的Datasheet PDF文件第2页浏览型号SN74LVTH373NSR的Datasheet PDF文件第3页浏览型号SN74LVTH373NSR的Datasheet PDF文件第4页浏览型号SN74LVTH373NSR的Datasheet PDF文件第5页浏览型号SN74LVTH373NSR的Datasheet PDF文件第6页浏览型号SN74LVTH373NSR的Datasheet PDF文件第7页 
SN74LV245AT  
OCTAL BUS TRANSCEIVER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCLS605B–DECEMBER 2004–REVISED AUGUST 2005  
FEATURES  
•
•
•
•
Inputs Are TTL-Voltage Compatible  
4.5-V to 5.5-V VCC Operation  
Typical tpd of 3.5 ns at 5 V  
•
•
•
Ioff Supports Partial-Power-Down Mode  
Operation  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
Typical VOLP (Output Ground Bounce) <0.8 V  
at VCC = 5 V, TA = 25°C  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
•
•
Typical VOHV (Output VOH Undershoot) >2.3 V  
at VCC = 5 V, TA = 25°C  
– 1000-V Charged-Device Model (C101)  
xxxxxxx  
Supports Mixed-Mode Voltage Operation on  
All Ports  
DB, DGV, DW, NS, OR PW PACKAGE  
(TOP VIEW)  
RGY PACKAGE  
(TOP VIEW)  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
DIR  
A1  
A2  
V
CC  
OE  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
1
20  
19  
18  
17  
16  
15  
14  
13  
12  
2
3
4
5
6
7
8
9
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
OE  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
A3  
A4  
A5  
A6  
A7  
A8  
GND  
10  
11  
DESCRIPTION/ORDERING INFORMATION  
This octal bus transceiver is designed for asynchronous two-way communication between data buses. The  
control-function implementation minimizes external timing requirements.  
The SN74LV245AT allows data transmission from the A bus to the B bus or from the B bus to the A bus,  
depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to  
disable the device so that the buses are effectively isolated.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
SN74LV245ATRGYR  
SN74LV245ATDW  
TOP-SIDE MARKING  
VV245  
QFN – RGY  
SOIC – DW  
Tape and reel  
Tube  
LV245A  
Tape and reel  
Tape and reel  
Tape and reel  
Tape and reel  
Tape and reel  
SN74LV245ATDWR  
SN74LV245ATNSR  
–40°C to 85°C  
SOP – NS  
74LV245A  
LV245A  
SSOP – DB  
TSSOP – PW  
TVSOP – DGV  
SN74LV245ATDBR  
SN74LV245ATPWR  
SN74LV245ATGVR  
LV245AT  
LV245A  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2004–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...19

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