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SN74LVTH16652MTD PDF预览

SN74LVTH16652MTD

更新时间： 2024-11-18 19:47:03
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 信息通信管理光电二极管逻辑集成电路
页数 文件大小 规格书
9页 87K
描述
Registered Bus Transceiver, LVT Series, 2-Func, 8-Bit, True Output, BICMOS, PDSO56, 6.10 MM, MO-153, TSSOP-56

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SN74LVTH16652MTD 技术参数

生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP,针数：56
Reach Compliance Code：unknown风险等级：5.3
系列：LVTJESD-30 代码：R-PDSO-G56
长度：14 mm逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
位数：8功能数量：2
端口数量：2端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
传播延迟（tpd）：5.4 ns认证状态：Not Qualified
座面最大高度：1.2 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：BICMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
宽度：6.1 mmBase Number Matches：1

SN74LVTH16652MTD 数据手册

 浏览型号SN74LVTH16652MTD的Datasheet PDF文件第2页浏览型号SN74LVTH16652MTD的Datasheet PDF文件第3页浏览型号SN74LVTH16652MTD的Datasheet PDF文件第4页浏览型号SN74LVTH16652MTD的Datasheet PDF文件第5页浏览型号SN74LVTH16652MTD的Datasheet PDF文件第6页浏览型号SN74LVTH16652MTD的Datasheet PDF文件第7页 
January 2000  
Revised January 2000  
74LVTH16652  
Low Voltage 16-Bit Transceiver/Register  
with 3-STATE Outputs  
General Description  
Features  
■ Input and output interface capability to systems at  
The LVTH16652 consists of sixteen bus transceiver circuits  
with D-type flip-flops, and control circuitry arranged for mul-  
tiplexed transmission of data directly from the input bus or  
from the internal registers. Each byte has separate control  
inputs which can be shorted together for full 16-bit opera-  
tion. Data on the A or B bus will be clocked into the regis-  
ters as the appropriate clock pin goes to the HIGH logic  
level. Output Enable pins (OEAB, OEBA) are provided to  
control the transceiver function (see Functional Descrip-  
tion).  
5V VCC  
■ Bushold data inputs eliminate the need for external  
pull-up resistors to hold unused inputs  
■ Live insertion/extraction permitted  
■ Power Up/Down high impedance provides glitch-free  
bus loading  
■ Outputs source/sink −32 mA/+64 mA  
■ Functionally compatible with the 74 series 16652  
■ Latch-up performance exceeds 500 mA  
The LVTH16652 data inputs include bushold, eliminating  
the need for external pull-up resistors to hold unused  
inputs.  
The transceivers are designed for low-voltage (3.3V) VCC  
applications, but with the capability to provide a TTL inter-  
face to a 5V environment. The LVTH16652 is fabricated  
with an advanced BiCMOS technology to achieve high  
speed operation similar to 5V ABT while maintaining low  
power dissipation.  
Ordering Code:  
Order Number Package Number  
Package Description  
74LVTH16652MEA  
74LVTH16652MTD  
MS56A  
MTD56  
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
© 2000 Fairchild Semiconductor Corporation  
DS012024  
www.fairchildsemi.com  
1234567...9

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