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SN74LVTH182504APM

更新时间： 2024-09-09 23:09:43
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路测试信息通信管理
页数 文件大小 规格书
35页 544K
描述
3.3-V ABT SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS

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中文翻译

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SN74LVTH182504APM 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：QFP
包装说明：QFP-64针数：64
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：1.29Is Samacsys：N
其他特性：SCANNABLE控制类型：INDEPENDENT CONTROL
计数方向：BIDIRECTIONAL系列：LVT
JESD-30 代码：S-PQFP-G64JESD-609代码：e4
长度：10 mm负载电容（CL）：50 pF
逻辑集成电路类型：BOUNDARY SCAN REG BUS TRANSCEIVER最大I（ol）：0.064 A
湿度敏感等级：3位数：20
功能数量：1端口数量：2
端子数量：64最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE WITH SERIES RESISTOR
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：LFQFP封装等效代码：QFP64,.47SQ,20
封装形状：SQUARE封装形式：FLATPACK, LOW PROFILE, FINE PITCH
包装方法：TRAY峰值回流温度（摄氏度）：260
电源：3.3 V最大电源电流（ICC）：27 mA
Prop。Delay @ Nom-Sup：5.9 ns传播延迟（tpd）：7.7 ns
认证状态：Not Qualified座面最大高度：1.6 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：BICMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
翻译：N/A宽度：10 mm
Base Number Matches：1

SN74LVTH182504APM 数据手册

 浏览型号SN74LVTH182504APM的Datasheet PDF文件第2页浏览型号SN74LVTH182504APM的Datasheet PDF文件第3页浏览型号SN74LVTH182504APM的Datasheet PDF文件第4页浏览型号SN74LVTH182504APM的Datasheet PDF文件第5页浏览型号SN74LVTH182504APM的Datasheet PDF文件第6页浏览型号SN74LVTH182504APM的Datasheet PDF文件第7页 
SN54LVTH18504A, SN54LVTH182504A, SN74LVTH18504A, SN74LVTH182504A  
3.3-V ABT SCAN TEST DEVICES  
WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS  
SCBS667B – JULY 1996 – REVISED JUNE 1997  
Members of the Texas Instruments  
SCOPE Family of Testability Products  
Compatible With the IEEE Std 1149.1-1990  
(JTAG) Test Access Port and  
Boundary-Scan Architecture  
Members of the Texas Instruments  
Widebus Family  
SCOPE Instruction Set  
– IEEE Std 1149.1-1990 Required  
Instructions and Optional CLAMP and  
HIGHZ  
– Parallel-Signature Analysis at Inputs  
– Pseudo-Random Pattern Generation  
From Outputs  
State-of-the-Art 3.3-V ABT Design Supports  
Mixed-Mode Signal Operation (5-V Input  
and Output Voltages With 3.3-V V  
)
CC  
Support Unregulated Battery Operation  
Down to 2.7 V  
UBT (Universal Bus Transceiver)  
Combines D-Type Latches and D-Type  
Flip-Flops for Operation in Transparent,  
Latched, or Clocked Mode  
– Sample Inputs/Toggle Outputs  
– Binary Count From Outputs  
– Device Identification  
– Even-Parity Opcodes  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
Packaged in 64-Pin Plastic Thin Quad Flat  
(PM) Packages Using 0.5-mm  
Center-to-Center Spacings and 68-Pin  
Ceramic Quad Flat (HV) Packages Using  
25-mil Center-to-Center Spacings  
B-Port Outputs of ’LVTH182504A Devices  
Have Equivalent 25-Ω Series Resistors, So  
No External Resistors Are Required  
description  
The ’LVTH18504A and ’LVTH182504A scan test devices with 20-bit universal bus transceivers are members  
of the Texas Instruments (TI) SCOPE testability integrated-circuit family. This family of devices supports  
IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to  
the test circuitry is accomplished via the 4-wire test access port (TAP) interface.  
Additionally, these devices are designed specifically for low-voltage (3.3-V) V  
capability to provide a TTL interface to a 5-V system environment.  
operation, but with the  
CC  
In the normal mode, these devices are 20-bit universal bus transceivers that combine D-type latches and D-type  
flip-flops to allow data flow in transparent, latched, or clocked modes. The test circuitry can be activated by the  
TAP to take snapshot samples of the data appearing at the device pins or to perform a self-test on the  
boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the  
SCOPE universal bus transceivers.  
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),  
clock-enable (CLKENAB and CLKENBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the  
device operates in the transparent mode when LEAB is high. When LEAB is low, the A-bus data is latched while  
CLKENAB is high and/or CLKAB is held at a static low or high logic level. Otherwise, if LEAB is low and  
CLKENAB is low, A-bus data is stored on a low-to-high transition of CLKAB. When OEAB is low, the B outputs  
are active. When OEAB is high, the B outputs are in the high-impedance state. B-to-A data flow is similar to  
A-to-B data flow, but uses the OEBA, LEBA, CLKENBA, and CLKBA inputs.  
Inthetestmode, thenormaloperationoftheSCOPEuniversalbustransceiversisinhibited, andthetestcircuitry  
is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs  
boundary-scan test operations according to the protocol described in IEEE Std 1149.1-1990.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
SCOPE, UBT, and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...35

中文翻译

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SN74LVTH182504APM 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVTH18504APMR TI

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 3.3-V ABT SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SN74LVTH18504APMG4 TI

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SN74LVTH18504APM TI

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