Datasheet > SN74LVC2G00DCTRG4

SN74LVC2G00DCTRG4

更新时间： 2024-11-20 06:12:59

品牌	Logo	应用领域
德州仪器 - TI		输入元件
页数	文件大小	规格书
13页	526K
描述
DUAL 2-INPUT POSITIVE-NAND GATE

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SN74LVC2G00

DUAL 2-INPUT POSITIVE-NAND GATE

www.ti.com

SCES193L–APRIL 1999–REVISED JANUARY 2007

FEATURES

•

Available in the Texas Instruments

NanoFree™ Package

•

Typical V_OHV(Output V_OHUndershoot)

>2 V at V_CC= 3.3 V, T_A= 25°C

•

Supports 5-V V_CCOperation

I_offSupports Partial-Power-Down Mode

Operation

Inputs Accept Voltages to 5.5 V

Max t_pdof 4.3 ns at 3.3 V

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

Low Power Consumption, 10-µA Max I_CC

±24-mA Output Drive at 3.3 V

ESD Protection Exceeds JESD 22

–

2000-V Human-Body Model (A114-A)

1000-V Charged-Device Model (C101)

Typical V_OLP(Output Ground Bounce)

<0.8 V at V_CC= 3.3 V, T_A= 25°C

DCT PACKAGE

(TOP VIEW)

DCU PACKAGE

(TOP VIEW)

YZP PACKAGE

(BOTTOM VIEW)

4 5

GND

V_CC

3 6

2 7

1 8

V_CC

GND

See mechanical drawings for dimensions.

DESCRIPTION/ORDERING INFORMATION

This dual 2-input positive-NAND gate is designed for 1.65-V to 5.5-V V_CCoperation.

The SN74LVC2G00 performs the Boolean function Y = A B or Y = A + B in positive logic.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the

package.

This device is fully specified for partial-power-down applications using I_off. The I_offcircuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.

ORDERING INFORMATION

T_A

PACKAGE⁽¹⁾

ORDERABLE PART NUMBER TOP-SIDE MARKING⁽²⁾

NanoFree™ – WCSP (DSBGA)

0.23-mm Large Bump – YZP (Pb-free)

SSOP – DCT

Reel of 3000

SN74LVC2G00YZPR

_ _ _CA_

C00_ _ _

Reel of 3000

Reel of 250

SN74LVC2G00DCTR

SN74LVC2G00DCUR

SN74LVC2G00DCUT

–40°C to 85°C

VSSOP – DCU

C00_

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

(2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.

DCU: The actual top-side marking has one additional character that designates the assembly/test site.

YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following

character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

NanoFree is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7...13

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SN74LVC2G00DCTRG4 替代型号

型号	品牌	替代类型	描述	数据表
SN74LVC2G00DCTR	TI	功能相似	DUAL 2 INPUT POSITIVE NAND GATE

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