Datasheet > SN74LVC2G00W-EP

SN74LVC2G00W-EP

更新时间： 2024-11-21 02:58:23

品牌	Logo	应用领域
德州仪器 - TI		输入元件
页数	文件大小	规格书
9页	126K
描述
DUAL 2-INPUT POSITIVE-NAND GATE

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SN74LVC2G00W-EP 数据手册

SN74LVC2G00W-EP

DUAL 2-INPUT POSITIVE-NAND GATE

www.ti.com

SCES645–SEPTEMBER 2005

FEATURES

•

Controlled Baseline

•

±24-mA Output Drive at 3.3 V

– One Assembly/Test Site, One Fabrication

Site

Typical V_OLP(Output Ground Bounce)

<0.8 V at V_CC= 3.3 V, T_A= 25°C

•

Extended Temperature Performance of –55°C

to 115°C

•

Typical V_OHV(Output V_OHUndershoot)

>2 V at V_CC= 3.3 V, T_A= 25°C

Enhanced Diminishing Manufacturing

Sources (DMS) Support

I_offSupports Partial-Power-Down Mode

Operation

•

Enhanced Product-Change Notification

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

(1)

Qualification Pedigree

ESD Protection Exceeds JESD 22

Supports 5-V V_CCOperation

– 2000-V Human-Body Model (A114-A)

– 1000-V Charged-Device Model (C101)

Inputs Accept Voltages to 5.5 V

Max t_pdof 5.3 ns at 3.3 V

Low Power Consumption, 10-µA Max I_CC

DCT PACKAGE

(TOP VIEW)

(1) Component qualification in accordance with JEDEC and

industry standards to ensure reliable operation over an

extended temperature range. This includes, but is not limited

to, Highly Accelerated Stress Test (HAST) or biased 85/85,

temperature cycle, autoclave or unbiased HAST,

electromigration, bond intermetallic life, and mold compound

life. Such qualification testing should not be viewed as

justifying use of this component beyond specified

performance and environmental limits.

GND

DESCRIPTION/ORDERING INFORMATION

This dual 2-input positive-NAND gate is designed for 1.65-V to 5.5-V V_CCoperation.

The SN74LVC2G00W-EP performs the Boolean function Y = A • B or Y = A + B in positive logic.

This device is fully specified for partial-power-down applications using I_off. The I_offcircuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.

ORDERING INFORMATION

T_A

PACKAGE⁽¹⁾

ORDERABLE PART NUMBER

TOP-SIDE MARKING⁽²⁾

–55°C to 115°C

SSOP – DCT

Reel of 3000

SN74LVC2G00WDCTREP

C00_ _ _

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

(2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7...9

中文翻译

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