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SN74LVC1G00MDCKREP

更新时间： 2024-11-02 12:15:03
品牌 Logo 应用领域
德州仪器 - TI 输入元件
页数 文件大小 规格书
14页 483K
描述
SINGLE 2-INPUT POSITIVE-NAND GATE

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SN74LVC1G00MDCKREP 数据手册

 浏览型号SN74LVC1G00MDCKREP的Datasheet PDF文件第2页浏览型号SN74LVC1G00MDCKREP的Datasheet PDF文件第3页浏览型号SN74LVC1G00MDCKREP的Datasheet PDF文件第4页浏览型号SN74LVC1G00MDCKREP的Datasheet PDF文件第5页浏览型号SN74LVC1G00MDCKREP的Datasheet PDF文件第6页浏览型号SN74LVC1G00MDCKREP的Datasheet PDF文件第7页 
SN74LVC1G00-EP  
SINGLE 2-INPUT POSITIVE-NAND GATE  
www.ti.com  
SCES450D–DECEMBER 2003–REVISED SEPTEMBER 2006  
FEATURES  
•
Controlled Baseline  
•
•
•
Ioff Supports Partial-Power-Down Mode  
Operation  
– One Assembly/Test Site, One Fabrication  
Site  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
•
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
•
•
•
•
•
•
•
Enhanced Product-Change Notification  
(1)  
Qualification Pedigree  
Supports 5-V VCC Operation  
– 1000-V Charged-Device Model (C101)  
Inputs Accept Voltages to 5.5 V  
Max tpd of 3.8 ns at 3.3 V  
DBV OR DCK PACKAGE  
(TOP VIEW)  
Low Power Consumption, 10-µA Max ICC  
±24-mA Output Drive at 3.3 V  
1
2
3
5
4
A
B
V
Y
CC  
(1) Component qualification in accordance with JEDEC and  
industry standards to ensure reliable operation over an  
extended temperature range. This includes, but is not limited  
to, Highly Accelerated Stress Test (HAST) or biased 85/85,  
temperature cycle, autoclave or unbiased HAST,  
GND  
electromigration, bond intermetallic life, and mold compound  
life. Such qualification testing should not be viewed as  
justifying use of this component beyond specified  
performance and environmental limits.  
DESCRIPTION/ORDERING INFORMATION  
This single 2-input positive-NAND gate is designed for 1.65-V to 5.5-V VCC operation.  
The SN74LVC1G00 performs the Boolean function Y = A • B or Y = A + B in positive logic.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
SN74LVC1G00IDCKREP  
SN74LVC1G00MDBVREP  
SN74LVC1G00MDCKREP  
TOP-SIDE MARKING(2)  
CAO  
–40°C to 85°C  
SOP (SC-70) – DCK  
Reel of 3000  
Reel of 3000  
Reel of 3000  
SOP – DBV  
SBFM  
BYA  
–55°C to 125°C  
SOP (SC-70) – DCK  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
(2) The actual top-side marking has one additional character that designates the assembly/test site.  
FUNCTION TABLE  
INPUTS  
OUTPUT  
Y
A
H
L
B
H
X
L
L
H
H
X
LOGIC DIAGRAM (POSITIVE LOGIC)  
1
A
B
4
Y
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2003–2006, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...14

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SN74LVC1G00MDCKREP 替代型号

型号 品牌 替代类型 描述 数据表
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