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SN74LVC1G02ADCKR PDF预览

SN74LVC1G02ADCKR

更新时间： 2024-11-02 13:00:35
品牌 Logo 应用领域
德州仪器 - TI 输入元件
页数 文件大小 规格书
16页 664K
描述
LVC/LCX/Z SERIES, 2-INPUT NOR GATE, PDSO5, PLASTIC, SO-5

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SN74LVC1G02ADCKR 技术参数

生命周期：Obsolete零件包装代码：SOIC
包装说明：TSSOP, TSSOP5/6,.08针数：5
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.21系列：LVC/LCX/Z
JESD-30 代码：R-PDSO-G5长度：2 mm
逻辑集成电路类型：NOR GATE功能数量：1
输入次数：2端子数量：5
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP5/6,.08封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH认证状态：Not Qualified
座面最大高度：1.1 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：1.65 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL宽度：1.25 mm
Base Number Matches：1

SN74LVC1G02ADCKR 数据手册

 浏览型号SN74LVC1G02ADCKR的Datasheet PDF文件第2页浏览型号SN74LVC1G02ADCKR的Datasheet PDF文件第3页浏览型号SN74LVC1G02ADCKR的Datasheet PDF文件第4页浏览型号SN74LVC1G02ADCKR的Datasheet PDF文件第5页浏览型号SN74LVC1G02ADCKR的Datasheet PDF文件第6页浏览型号SN74LVC1G02ADCKR的Datasheet PDF文件第7页 
SN74LVC1G02  
SINGLE 2-INPUT POSITIVE NOR-GATE  
www.ti.com  
SCES213R–APRIL 1999–REVISED JANUARY 2007  
FEATURES  
•
Available in the Texas Instruments  
NanoFree™ Package  
•
•
•
Ioff Supports Partial-Power-Down Mode  
Operation  
•
•
•
•
•
Supports 5-V VCC Operation  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
Inputs Accept Voltages to 5.5 V  
Max tpd of 3.6 ns at 3.3 V  
ESD Protection Exceeds JESD 22  
–
–
–
2000-V Human-Body Model (A114-A)  
200-V Machine Model (A115-A)  
Low Power Consumption, 10-µA Max ICC  
±24-mA Output Drive at 3.3 V  
1000-V Charged-Device Model (C101)  
YZP PACKAGE  
(BOTTOM VIEW)  
DBV PACKAGE  
(TOP VIEW)  
DCK PACKAGE  
(TOP VIEW)  
DRL PACKAGE  
(TOP VIEW)  
3
2
1
4
5
GND  
B
Y
VCC  
1
2
3
5
VCC  
A
B
1
2
3
5
A
VCC  
1
2
3
5
4
A
B
B
VCC  
A
4
GND  
Y
4
GND  
Y
GND  
Y
See mechanical drawings for dimensions.  
DESCRIPTION/ORDERING INFORMATION  
This single 2-input positive-NOR gate is designed for 1.65-V to 5.5-V VCC operation.  
The SN74LVC1G02 performs the Boolean function Y = A + B or Y = A•B in positive logic.  
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the  
package.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING(2)  
_ _ _ CB_  
NanoFree™ – WCSP (DSBGA)  
0.23-mm Large Bump – YZP  
(Pb-free)  
SN74LVC1G02YZPR  
Reel of 3000 SN74LVC1G02DBVR  
Reel of 250 SN74LVC1G02DBVT  
Reel of 3000 SN74LVC1G02DCKR  
Reel of 250 SN74LVC1G02DCKT  
Reel of 4000 SN74LVC1G02DRLR  
SOT (SOT-23) – DBV  
C02_  
–40°C to 85°C  
SOT (SC-70) – DCK  
CB_  
CB_  
SOT (SOT-553) – DRL  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
(2) DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site.  
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following  
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoFree is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1999–2007, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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