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SN74LV125DR PDF预览

SN74LV125DR

更新时间: 2024-01-05 03:54:35
品牌 Logo 应用领域
德州仪器 - TI 输出元件
页数 文件大小 规格书
7页 119K
描述
QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

SN74LV125DR 技术参数

生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP14,.25针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.2系列:LV/LV-A/LVX/H
JESD-30 代码:R-PDSO-G14长度:5 mm
逻辑集成电路类型:BUS DRIVER位数:1
功能数量:4端口数量:2
端子数量:14最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
传播延迟(tpd):23 ns认证状态:Not Qualified
座面最大高度:1.2 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
宽度:4.4 mmBase Number Matches:1

SN74LV125DR 数据手册

 浏览型号SN74LV125DR的Datasheet PDF文件第2页浏览型号SN74LV125DR的Datasheet PDF文件第3页浏览型号SN74LV125DR的Datasheet PDF文件第4页浏览型号SN74LV125DR的Datasheet PDF文件第5页浏览型号SN74LV125DR的Datasheet PDF文件第6页浏览型号SN74LV125DR的Datasheet PDF文件第7页 
ꢊ ꢋꢌꢍꢎ ꢋꢏꢄ ꢐ ꢑꢋꢀ ꢑꢋꢒ ꢒ ꢐꢎ ꢓ ꢌꢔꢐ  
SCES003B − NOVEMBER 1994 − REVISED APRIL 1996  
SN54LV125 . . . J OR W PACKAGE  
SN74LV125 . . . D, DB, OR PW PACKAGE  
(TOP VIEW)  
D
D
D
D
EPIC(Enhanced-Performance Implanted  
CMOS) 2-µ Process  
Typical V  
(Output Ground Bounce)  
OLP  
< 0.8 V at V , T = 25°C  
CC  
A
1OE  
1A  
V
CC  
4OE  
4A  
1
2
3
4
5
6
7
14  
13  
12  
11  
Typical V  
(Output V  
Undershoot)  
OHV  
OH  
> 2 V at V , T = 25°C  
1Y  
CC  
A
2OE  
2A  
4Y  
ESD Protection Exceeds 2000 V per  
MIL-STD-883C, Method 3015; Exceeds  
200 V Using Machine Model  
(C = 200 pF, R = 0)  
10 3OE  
9
8
2Y  
3A  
3Y  
GND  
D
D
Latch-Up Performance Exceeds 250 mA  
Per JEDEC Standard JESD-17  
SN54LV125 . . . FK PACKAGE  
(TOP VIEW)  
Package Options Include Plastic  
Small-Outline (D), Shrink Small-Outline  
(DB), Thin Shrink Small-Outline (PW),  
Ceramic Flat (W) Packages, Chip Carriers  
(FK), and (J) 300-mil DIPs  
3
2
1
20 19  
18  
4A  
NC  
4Y  
1Y  
NC  
4
5
6
7
8
17  
16  
description  
2OE  
NC  
15 NC  
14  
9 10 11 12 13  
These quadruple bus buffer gates are designed  
for 2.7-V to 5.5-V V operation.  
3OE  
2A  
CC  
The ’LV125 feature independent line drivers with  
3-state outputs. Each output is disabled when the  
associated output-enable (OE) input is high.  
NC − No internal connection  
The SN54LV125 is characterized for operation  
over the full military temperature range of −55°C  
to 125°C. The SN74LV125 is characterized for  
operation from −40°C to 85°C.  
FUNCTION TABLE  
(each buffer)  
INPUTS  
OUTPUT  
Y
H
L
OE  
A
H
L
L
L
H
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
ꢋ ꢁ ꢄꢐꢀꢀ ꢚ ꢔꢗ ꢐꢎꢕ ꢖꢀ ꢐ ꢁ ꢚꢔꢐꢍ ꢛꢜ ꢝꢞ ꢟꢠꢡ ꢢꢣꢤ ꢥꢛ ꢡꢠ ꢥꢛꢦ ꢝꢥꢞ ꢏꢎ ꢚ ꢍ ꢋ ꢧꢔ ꢖꢚ ꢁ  
ꢪꢦ ꢩ ꢦ ꢣ ꢤ ꢛ ꢤ ꢩ ꢞ ꢭ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  

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