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SN74LV126ADGV PDF预览

SN74LV126ADGV

更新时间： 2024-01-17 05:58:03
品牌 Logo 应用领域
德州仪器 - TI 输出元件
页数 文件大小 规格书
7页 130K
描述
QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

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SN74LV126ADGV 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP, TSSOP14,.25针数：14
Reach Compliance Code：compliantHTS代码：8542.39.00.01
Factory Lead Time：6 weeks风险等级：1.4
控制类型：ENABLE HIGH计数方向：UNIDIRECTIONAL
系列：LV/LV-A/LVX/HJESD-30 代码：R-PDSO-G14
JESD-609代码：e4长度：5 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS DRIVER
最大I（ol）：0.016 A湿度敏感等级：1
位数：1功能数量：4
端口数量：2端子数量：14
最高工作温度：125 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP14,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法：TR
峰值回流温度（摄氏度）：260电源：3.3 V
最大电源电流（ICC）：0.02 mAProp。Delay @ Nom-Sup：13 ns
传播延迟（tpd）：18.5 ns认证状态：Not Qualified
座面最大高度：1.2 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：AUTOMOTIVE
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：N/A
宽度：4.4 mmBase Number Matches：1

SN74LV126ADGV 数据手册

 浏览型号SN74LV126ADGV的Datasheet PDF文件第2页浏览型号SN74LV126ADGV的Datasheet PDF文件第3页浏览型号SN74LV126ADGV的Datasheet PDF文件第4页浏览型号SN74LV126ADGV的Datasheet PDF文件第5页浏览型号SN74LV126ADGV的Datasheet PDF文件第6页浏览型号SN74LV126ADGV的Datasheet PDF文件第7页 
SN54LV126A, SN74LV126A  
QUADRUPLE BUS BUFFER GATES  
WITH 3-STATE OUTPUTS  
SCES131C – MARCH 1998 – REVISED JULY 1998  
SN54LV126A . . . J OR W PACKAGE  
SN74LV126A . . . D, DB, DGV, NS, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) Process  
Typical V  
< 0.8 V at V , T = 25°C  
(Output Ground Bounce)  
OLP  
CC  
A
1OE  
1A  
V
CC  
4OE  
4A  
1
2
3
4
5
6
7
14  
13  
12  
11  
Typical V  
> 2 V at V , T = 25°C  
(Output V  
Undershoot)  
OHV  
CC  
OH  
1Y  
A
2OE  
2A  
4Y  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
10 3OE  
2Y  
9
8
3A  
3Y  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
GND  
SN54LV126A . . . FK PACKAGE  
(TOP VIEW)  
Package Options Include Plastic  
Small-Outline (D, NS), Shrink Small-Outline  
(DB), Thin Very Small-Outline (DGV), and  
Thin Shrink Small-Outline (PW) Packages,  
Ceramic Flat (W) Packages, Chip Carriers  
(FK), and DIPs (J)  
3
2
1
20 19  
18  
4
5
6
7
8
1Y  
NC  
4A  
17  
16  
15  
14  
NC  
4Y  
description  
2OE  
NC  
NC  
3OE  
These quadruple bus buffer gates are designed  
for 2-V to 5.5-V V operation.  
2A  
9 10 11 12 13  
CC  
The ’LV126A devices feature independent line  
drivers with 3-state outputs. Each output is  
disabled when the associated output-enable (OE)  
input is low.  
NC – No internal connection  
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a  
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the  
driver.  
The SN54LV126A is characterized for operation over the full military temperature range of –55°C to 125°C. The  
SN74LV126A is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
(each buffer)  
INPUTS  
OUTPUT  
Y
OE  
A
H
L
H
H
L
H
L
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1998, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567

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