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SN74LV126ADGVRG4 PDF预览

SN74LV126ADGVRG4

更新时间: 2024-01-26 22:35:28
品牌 Logo 应用领域
德州仪器 - TI 输出元件
页数 文件大小 规格书
17页 396K
描述
QUADRUPLE BUS BUFFER GATES WITH 3 STATE OUTPUTS

SN74LV126ADGVRG4 数据手册

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ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢈ ꢉꢊ ꢀꢁꢋ ꢃꢄꢅ ꢆꢇ ꢈꢉ  
ꢌ ꢍꢉꢎꢏ ꢍꢐꢄ ꢑ ꢒꢍꢀ ꢒꢍꢓ ꢓ ꢑꢏ ꢔ ꢉꢕꢑ ꢀ  
ꢖ ꢗꢕ ꢘ ꢙ ꢚꢀꢕꢉꢕ ꢑ ꢛ ꢍꢕ ꢐꢍ ꢕꢀ  
SCES131H − MARCH 1998 − REVISED APRIL 2005  
SN54LV126A . . . J OR W PACKAGE  
SN74LV126A . . . D, DB, DGV, NS, OR PW PACKAGE  
(TOP VIEW)  
D
D
D
D
D
D
D
2-V to 5.5-V V  
Operation  
CC  
Max t of 6.5 ns at 5 V  
pd  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
1OE  
1A  
V
CC  
13 4OE  
= 3.3 V, T = 25°C  
1
2
3
4
5
6
7
14  
A
Typical V  
>2.3 V at V  
(Output V  
Undershoot)  
OHV  
CC  
OH  
12  
11  
10  
9
1Y  
4A  
= 3.3 V, T = 25°C  
A
2OE  
2A  
4Y  
Support Mixed-Mode Voltage Operation on  
All Ports  
3OE  
3A  
2Y  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
8
GND  
3Y  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
SN54LV126A . . . FK PACKAGE  
(TOP VIEW)  
− 1000-V Charged-Device Model (C101)  
description/ordering information  
3
2
1
20 19  
18  
1Y  
NC  
4A  
4
5
6
7
8
These quadruple bus buffer gates are designed  
17  
16  
15  
14  
NC  
4Y  
for 2-V to 5.5-V V  
operation.  
2OE  
NC  
CC  
NC  
3OE  
The ’LV126A devices feature independent line  
drivers with 3-state outputs. Each output is  
disabled when the associated output-enable (OE)  
input is low.  
2A  
9 10 11 12 13  
To ensure the high-impedance state during power  
up or power down, OE should be tied to GND  
through a pulldown resistor; the minimum value of  
the resistor is determined by the current-sourcing  
capability of the driver.  
NC − No internal connection  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
Tube of 50  
SN74LV126AD  
SOIC − D  
LV126A  
Reel of 2500  
Reel of 2000  
Reel of 2000  
Tube of 90  
SN74LV126ADR  
SN74LV126ANSR  
SN74LV126ADBR  
SN74LV126APW  
SN74LV126APWR  
SN74LV126APWT  
SN74LV126ADGVR  
SNJ54LV126AJ  
SOP − NS  
74LV126A  
LV126A  
SSOP − DB  
−40°C to 85°C  
Reel of 2000  
Reel of 250  
Reel of 2000  
Tube of 25  
TSSOP − PW  
LV126A  
TVSOP − DGV  
CDIP − J  
LV126A  
SNJ54LV126AJ  
SNJ54LV126AW  
SNJ54LV126AFK  
−55°C to 125°C  
CFP − W  
Tube of 150  
Tube of 55  
SNJ54LV126AW  
SNJ54LV126AFK  
LCCC − FK  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2005, Texas Instruments Incorporated  
ꢍ ꢁ ꢄꢑꢀꢀ ꢛ ꢕꢘ ꢑꢏꢖ ꢗꢀ ꢑ ꢁ ꢛꢕꢑꢎ ꢜꢝ ꢞꢟ ꢠꢡꢢ ꢣꢤꢥ ꢦꢜ ꢢꢡ ꢦꢜꢧ ꢞꢦꢟ ꢐꢏ ꢛ ꢎ ꢍ ꢨꢕ ꢗꢛ ꢁ  
ꢫꢧ ꢪ ꢧ ꢤ ꢥ ꢜ ꢥ ꢪ ꢟ ꢮ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74LV126ADGVRG4 替代型号

型号 品牌 替代类型 描述 数据表
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完全替代

QUADRUPLE BUS BUFFER GATES WITH 3 STATE OUTPUTS
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QUADRUPLE BUS BUFFER GATES WITH 3 STATE OUTPUTS

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