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SN74LV132ADG4 PDF预览

SN74LV132ADG4

更新时间： 2024-11-28 05:17:11
品牌 Logo 应用领域
德州仪器 - TI 触发器输入元件
页数 文件大小 规格书
15页 475K
描述
QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS

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SN74LV132ADG4 数据手册

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SCES338E − SEPTEMBER 2000 − REVISED APRIL 2005  
SN54LV10A . . . J OR W PACKAGE  
SN74LV10A . . . D, DB, DGV, NS, OR PW PACKAGE  
(TOP VIEW)  
D
D
D
D
D
D
D
2-V to 5.5-V V  
Operation  
CC  
Max t of 7 ns at 5 V  
pd  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1A  
1B  
2A  
2B  
2C  
V
CC  
= 3.3 V, T = 25°C  
A
1C  
1Y  
3C  
3B  
3A  
3Y  
Typical V  
>2.3 V at V  
(Output V  
Undershoot)  
OHV  
CC  
OH  
= 3.3 V, T = 25°C  
A
I
Supports Partial-Power-Down Mode  
off  
Operation  
2Y  
GND  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
8
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
SN54LV10A . . . FK PACKAGE  
(TOP VIEW)  
− 1000-V Charged-Device Model (C101)  
description/ordering information  
3
2
1
20 19  
18  
1Y  
NC  
3C  
2A  
NC  
2B  
4
5
6
7
8
These triple 3-input positive-NAND gates are  
17  
16  
designed for 2-V to 5.5-V V  
operation.  
CC  
15 NC  
14  
9 10 11 12 13  
NC  
2C  
The ’LV10A devices perform the Boolean function  
Y = A • B • C or Y = A + B + C in positive logic.  
3B  
These devices are fully specified for  
partial-power-down applications using I . The I  
off  
off  
circuitry disables the outputs, preventing  
damaging current backflow through the devices  
when they are powered down.  
NC − No internal connection  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
Tube of 50  
SN74LV10AD  
SOIC − D  
LV10A  
Reel of 2500  
Reel of 2000  
Reel of 2000  
Tube of 90  
SN74LV10ADR  
SN74LV10ANSR  
SN74LV10ADBR  
SN74LV10APW  
SN74LV10APWR  
SN74LV10APWT  
SN74LV10ADGVR  
SNJ54LV10AJ  
SOP − NS  
74LV10A  
LV10A  
SSOP − DB  
−40°C to 85°C  
Reel of 2000  
Reel of 250  
Reel of 2000  
Tube of 25  
TSSOP − PW  
LV10A  
TVSOP − DGV  
CDIP − J  
LV10A  
SNJ54LV10AJ  
SNJ54LV10AW  
SNJ54LV10AFK  
−55°C to 125°C CFP − W  
Tube of 150  
Tube of 55  
SNJ54LV10AW  
SNJ54LV10AFK  
LCCC − FK  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2005, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...15

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SN74LV132ADG4 替代型号

型号 品牌 替代类型 描述 数据表
SN74LV132ADR TI

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 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS
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 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS
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