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SN74LV132APW PDF预览

SN74LV132APW

更新时间: 2024-11-17 23:06:23
品牌 Logo 应用领域
德州仪器 - TI 栅极触发器逻辑集成电路光电二极管输入元件PC
页数 文件大小 规格书
13页 331K
描述
QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS

SN74LV132APW 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP, TSSOP14,.25针数:14
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:0.69Samacsys Confidence:
Samacsys Status:ReleasedSamacsys PartID:607019
Samacsys Pin Count:14Samacsys Part Category:Integrated Circuit
Samacsys Package Category:OtherSamacsys Footprint Name:SOP65P640X120-14N
Samacsys Released Date:2017-01-12 12:59:53Is Samacsys:N
系列:LV/LV-A/LVX/HJESD-30 代码:R-PDSO-G14
JESD-609代码:e4长度:5 mm
负载电容(CL):50 pF逻辑集成电路类型:NAND GATE
最大I(ol):0.012 A湿度敏感等级:1
功能数量:4输入次数:2
端子数量:14最高工作温度:125 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP14,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TUBE
峰值回流温度(摄氏度):260电源:3.3 V
最大电源电流(ICC):0.02 mAProp。Delay @ Nom-Sup:17.5 ns
传播延迟(tpd):23 ns认证状态:Not Qualified
施密特触发器:YES座面最大高度:1.2 mm
子类别:Gate最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mmBase Number Matches:1

SN74LV132APW 数据手册

 浏览型号SN74LV132APW的Datasheet PDF文件第2页浏览型号SN74LV132APW的Datasheet PDF文件第3页浏览型号SN74LV132APW的Datasheet PDF文件第4页浏览型号SN74LV132APW的Datasheet PDF文件第5页浏览型号SN74LV132APW的Datasheet PDF文件第6页浏览型号SN74LV132APW的Datasheet PDF文件第7页 
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ꢌ ꢍꢉꢎꢏ ꢍꢐꢄ ꢑ ꢐꢒ ꢀꢓ ꢔ ꢓꢅꢑ ꢕꢁꢉꢁ ꢎ ꢖ ꢉꢔꢑ ꢀ  
ꢗ ꢓꢔ ꢘ ꢀꢙ ꢘꢚꢓ ꢔꢔꢕꢔ ꢏꢓꢖ ꢖ ꢑ ꢏ ꢓ ꢁꢐ ꢍ ꢔꢀ  
SCLS394H − APRIL 1998 − REVISED APRIL 2005  
SN54LV132A . . . J OR W PACKAGE  
SN74LV132A . . . D, DB, DGV, NS, OR PW PACKAGE  
(TOP VIEW)  
D
D
D
D
D
D
D
2-V to 5.5-V V  
Operation  
CC  
Max t of 9 ns at 5 V  
pd  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
1A  
1B  
V
CC  
13 4B  
1
2
3
4
5
6
7
14  
= 3.3 V, T = 25°C  
A
Typical V  
>2.3 V at V  
(Output V  
Undershoot)  
OHV  
CC  
OH  
12  
11  
10  
9
1Y  
4A  
4Y  
3B  
3A  
3Y  
= 3.3 V, T = 25°C  
A
2A  
Support Mixed-Mode Voltage Operation on  
All Ports  
2B  
2Y  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
8
GND  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
SN54LV132A . . . FK PACKAGE  
(TOP VIEW)  
− 1000-V Charged-Device Model (C101)  
description/ordering information  
3
2
1 20 19  
18  
4A  
17 NC  
1Y  
NC  
2A  
4
5
6
7
8
The  
positive-NAND gates designed for 2-V to 5.5-V  
operation.  
’LV132A  
devices  
are  
quadruple  
16  
4Y  
NC  
3B  
V
15  
14  
NC  
2B  
CC  
The ’LV132A devices perform the Boolean  
function Y = A B or Y = A + B in positive logic.  
9 10 11 12 13  
Each circuit functions as a NAND gate, but  
because of the Schmitt action, it has different input  
threshold levels for positive- and negative-going  
signals.  
NC − No internal connection  
These circuits are temperature compensated and  
can be triggered from the slowest of input ramps  
and still give clean jitter-free output signals.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
Tube of 25  
SN74LV132AD  
SOIC − D  
LV132A  
Reel of 2500  
Reel of 2000  
Reel of 2000  
Tube of 90  
SN74LV132ADR  
SN74LV132ANSR  
SN74LV132ADBR  
SN74LV132APW  
SN74LV132APWR  
SN74LV132APWT  
SN74LV132ADGVR  
SNJ54LV132AJ  
SOP − NS  
74LV132A  
LV132A  
SSOP − DB  
−40°C to 85°C  
Reel of 2000  
Reel of 250  
Reel of 2000  
Tube of 25  
TSSOP − PW  
LV132A  
TVSOP − DGV  
CDIP − J  
LV132A  
SNJ54LV132AJ  
SNJ54LV132AW  
SNJ54LV132AFK  
−55°C to 125°C  
CFP − W  
Tube of 150  
Tube of 55  
SNJ54LV132AW  
SNJ54LV132AFK  
LCCC - FK  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2005, Texas Instruments Incorporated  
ꢍ ꢁ ꢄꢑꢀꢀ ꢒ ꢔꢘ ꢑꢏꢗ ꢓꢀ ꢑ ꢁ ꢒꢔꢑꢎ ꢛꢜ ꢝꢞ ꢟꢠꢡ ꢢꢣꢤ ꢥꢛ ꢡꢠ ꢥꢛꢦ ꢝꢥꢞ ꢐꢏ ꢒ ꢎ ꢍ ꢙꢔ ꢓꢒ ꢁ  
ꢯꢬ  
ꢩꢦ ꢨ ꢦ ꢣ ꢤ ꢛ ꢤ ꢨ ꢞ ꢬ  
ꢡꢤ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74LV132APW 替代型号

型号 品牌 替代类型 描述 数据表
SN74LV132APWRG4 TI

完全替代

QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS
SN74LV132APWE4 TI

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QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS
SN74LV132APWR TI

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