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SN74LS76AJDS PDF预览

SN74LS76AJDS

更新时间: 2024-09-13 13:13:51
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 触发器
页数 文件大小 规格书
2页 68K
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SN74LS76AJDS 数据手册

 浏览型号SN74LS76AJDS的Datasheet PDF文件第2页 
SN54/74LS76A  
DUAL JK FLIP-FLOP  
WITH SET AND CLEAR  
The SN54/74LS76A offers individual J, K, Clock Pulse, Direct Set and Di-  
rect Clear inputs. These dual flip-flops are designed so that when the clock  
goes HIGH, the inputs are enabled and data will be accepted. The Logic Level  
of the J and K inputs will perform according to the Truth Table as long as mini-  
mum set-up times are observed. Input data is transferred to the outputs on the  
HIGH-to-LOW clock transitions.  
DUAL JK FLIP-FLOP  
WITH SET AND CLEAR  
LOW POWER SCHOTTKY  
J SUFFIX  
CERAMIC  
MODE SELECT — TRUTH TABLE  
CASE 620-09  
INPUTS  
OUTPUTS  
16  
OPERATING MODE  
1
S
D
C
J
K
Q
Q
D
Set  
L
H
L
H
H
H
H
H
L
L
H
H
H
H
X
X
X
h
l
X
X
X
h
h
l
H
L
H
q
L
H
q
L
H
H
q
H
L
Reset (Clear)  
*Undetermined  
Toggle  
Load “0” (Reset)  
Load “1” (Set)  
Hold  
N SUFFIX  
PLASTIC  
CASE 648-08  
16  
h
l
l
q
1
*Both outputs will be HIGH while both S and C are LOW, but the output states are unpredictable  
D
D
if S and C go HIGH simultaneously.  
D
D
H,h = HIGH Voltage Level  
L,l = LOW Voltage Level  
X = Immaterial  
l, h (q) = Lower case letters indicate the state of the referenced input (or output) one setup time prior  
to the HIGH-to-LOW clock transition  
D SUFFIX  
SOIC  
CASE 751B-03  
16  
1
ORDERING INFORMATION  
SN54LSXXJ  
SN74LSXXN  
SN74LSXXD  
Ceramic  
Plastic  
SOIC  
LOGIC DIAGRAM  
LOGIC SYMBOL  
2
7
Q
Q
S
S
D
D
15  
14  
11  
10  
16  
1
K
Q
Q
12  
6
K
Q
Q
CP  
J
CP  
J
CLEAR (C  
)
SET (S )  
D
D
4
9
C
C
D
K
J
D
3
8
V
= PIN 5  
CLOCK (CP)  
CC  
GND = PIN 13  
FAST AND LS TTL DATA  
5-79  

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