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SN74LS77

更新时间： 2024-10-31 23:03:15
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 锁存器
页数 文件大小 规格书
4页 74K
描述
4-BIT D LATCH LOW POWER SCHOTTKY

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中文翻译

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SN74LS77 数据手册

 浏览型号SN74LS77的Datasheet PDF文件第2页浏览型号SN74LS77的Datasheet PDF文件第3页浏览型号SN74LS77的Datasheet PDF文件第4页 
SN54/74LS75  
SN54/74LS77  
4-BIT D LATCH  
The TTL/MSI SN54/74LS75 and SN54/74LS77 are latches used as tem-  
porary storage for binary information between processing units and input/out-  
put or indicator units. Information present at a data (D) input is transferred to  
the Q output when the Enable is HIGH and the Q output will follow the data  
input as long as the Enable remains HIGH. When the Enable goes LOW, the  
information (that was present at the data input at the time the transition oc-  
curred) is retained at the Q output until the Enable is permitted to go HIGH.  
The SN54/74LS75 features complementary Q and Q output from a 4-bit  
latch and is available in the 16-pin packages. For higher component density  
applications the SN54/74LS77 4-bit latch is available in the 14-pin package  
with Q outputs omitted.  
4-BIT D LATCH  
LOW POWER SCHOTTKY  
CONNECTION DIAGRAMS DIP (TOP VIEW)  
J SUFFIX  
CERAMIC  
CASE 620-09  
Q
Q
Q
E
GND  
12  
Q
Q
Q
3
0
1
1
0–1  
13  
2
2
16  
15  
14  
11  
10  
9
16  
16  
1
SN54/74LS75  
N SUFFIX  
PLASTIC  
CASE 648-08  
1
2
3
4
5
6
8
7
1
Q
D
D
E
V
D
D
Q
3
0
0
1
2–3  
CC  
2
3
Q
Q
E
GND  
11  
NC  
10  
Q
Q
3
0
1
0–1  
12  
2
D SUFFIX  
SOIC  
CASE 751B-03  
14  
13  
9
8
16  
1
SN54/74LS77  
J SUFFIX  
CERAMIC  
CASE 632-08  
1
2
3
4
5
6
7
NC  
14  
D
D
E
V
D
D
3
0
1
2–3  
CC  
2
1
PIN NAMES  
LOADING (Note a)  
HIGH  
LOW  
N SUFFIX  
PLASTIC  
CASE 646-06  
D –D  
Data Inputs  
0.5 U.L.  
2.0 U.L.  
2.0 U.L.  
10 U.L.  
10 U.L.  
0.25 U.L.  
1.0 U.L.  
1.0 U.L.  
5 (2.5) U.L.  
5 (2.5) U.L.  
1
4
E
E
Q –Q  
Enable Input Latches 0, 1  
Enable Input Latches 2, 3  
Latch Outputs (Note b)  
0–1  
2–3  
1
14  
1
4
4
Q –Q  
Complimentary Latch Outputs (Note b)  
1
NOTES:  
a) 1 Unit Load (U.L.) = 40 µA HIGH.  
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)  
Temperature Ranges.  
D SUFFIX  
SOIC  
CASE 751A-02  
14  
1
TRUTH TABLE  
(Each latch)  
ORDERING INFORMATION  
NOTES:  
= bit time before enable  
t
n
t
n+1  
SN54LSXXJ  
SN74LSXXN  
SN74LSXXD  
Ceramic  
Plastic  
SOIC  
t
n
negative-going transition  
= bit time after enable  
D
H
L
Q
H
L
t
n+1  
negative-going transition  
FAST AND LS TTL DATA  
5-1  
1234

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与SN74LS77相关器件

型号 品牌 获取价格 描述 数据表
SN74LS77D MOTOROLA

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 		LS SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDSO14, SOIC-14
SN74LS77DR2 MOTOROLA

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 		LS SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDSO14, PLASTIC, SOIC-14
SN74LS77JD MOTOROLA

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 		LS SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, TRUE OUTPUT, CDIP14, CERAMIC, DIP-14
SN74LS77JDS MOTOROLA

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 		LS SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, TRUE OUTPUT, CDIP14, CERAMIC, DIP-14
SN74LS77JS MOTOROLA

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 		LS SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, TRUE OUTPUT, CDIP14, CERAMIC, DIP-14
SN74LS77N MOTOROLA

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 		LS SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDIP14, PLASTIC, DIP-14
SN74LS77ND MOTOROLA

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 		D Latch, LS Series, 2-Func, High Level Triggered, 2-Bit, True Output, TTL, PDIP14
SN74LS77NDS MOTOROLA

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 		LS SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDIP14
SN74LS77NS MOTOROLA

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 		LS SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDIP14
SN74LS77W MOTOROLA

获取价格

 		D Latch, 1-Func, 4-Bit, TTL, CDFP14

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