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SN74GTL16616_06

更新时间： 2024-11-06 04:13:47
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14页 161K
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17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS

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SN74GTL16616_06 数据手册

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SN74GTL16616  
17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER  
WITH BUFFERED CLOCK OUTPUTS  
www.ti.com  
SCBS481H–JUNE 1994–REVISED APRIL 2005  
FEATURES  
DGG OR DL PACKAGE  
•
Member of the Texas Instruments Widebus™  
(TOP VIEW)  
Family  
OEAB  
LEAB  
A1  
GND  
A2  
A3  
(3.3 V)  
A4  
CEAB  
CLKAB  
1
2
3
4
5
6
7
8
9
56  
55  
•
UBT™ Transceiver Combines D-Type Latches  
and D-Type Flip-Flops for Operation in  
Transparent, Latched, Clocked, or  
Clock-Enabled Modes  
54 B1  
GND  
53  
52  
51  
50  
B2  
B3  
V
•
OEC™ Circuitry Improves Signal Integrity and  
Reduces Electromagnetic Interference  
V
CC  
(5 V)  
CC  
•
•
GTL Buffered CLKAB Signal (CLKOUT)  
49 B4  
48 B5  
47 B6  
Translates Between GTL/GTL+ Signal Levels  
and LVTTL Logic Levels  
A5  
A6 10  
•
Supports Mixed-Mode (3.3 V and 5 V) Signal  
Operation on A-Port and Control Inputs  
GND  
A7  
A8  
GND  
B7  
B8  
11  
12  
13  
46  
45  
44  
•
•
Equivalent to '16601 Function  
A9 14  
A10 15  
A11 16  
A12 17  
43 B9  
Ioff Supports Partial-Power-Down Mode  
Operation  
42 B10  
41 B11  
40 B12  
•
Bus Hold on Data Inputs Eliminates the Need  
for External Pullup/Pulldown Resistors on  
A Port  
GND  
GND  
18  
39  
A13 19  
A14 20  
38 B13  
37 B14  
36 B15  
•
•
•
Distributed VCC and GND Pins Minimize  
High-Speed Switching Noise  
A15 21  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
V
CC  
(3.3 V) 22  
A16 23  
35  
V
REF  
34 B16  
ESD Protection Exceeds JESD 22  
A17 24  
33 B17  
GND 25  
CLKIN 26  
OEBA 27  
LEBA 28  
32 GND  
31 CLKOUT  
30 CLKBA  
29 CEBA  
– 2000-V Human-Body Model (A114-A)  
DESCRIPTION/ORDERING INFORMATION  
The SN74GTL16616 is a 17-bit UBT™ transceiver that provides LVTTL-to-GTL/GTL+ and GTL/GTL+-to-LVTTL  
signal-level translation. Combined D-type flip-flops and D-type latches allow for transparent, latched, clocked,  
and clocked-enabled modes of data transfer identical to the '16601 function. Additionally, this device provides for  
a copy of CLKAB at GTL/GTL+ signal levels (CLKOUT) and conversion of a GTL/GTL+ clock to LVTTL logic  
levels (CLKIN). This device provides an interface between cards operating at LVTTL logic levels and a backplane  
operating at GTL/GTL+ signal levels. Higher-speed operation is a direct result of the reduced output swing  
(<1 V), reduced input threshold levels, and OEC™ circuitry.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
SN74GTL16616DL  
TOP-SIDE MARKING  
GTL16616  
Tube  
SSOP – DL  
TSSOP – DGG  
–40°C to 85°C  
Tape and reel  
Tape and reel  
SN74GTL16616DLR  
GTL16616  
GTL16616  
SN74GTL16616DGGR  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus, UBT, OEC are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1994–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...14

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