SN54GTL16923, SN74GTL16923
18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVERS
SCBS674E – AUGUST 1996 – REVISED NOVEMBER 1999
Members of the Texas Instruments
Widebus Family
Distributed V
Minimizes High-Speed Switching Noise
and GND-Pin Configuration
CC
D-Type Flip-Flops With Qualified Storage
Enable
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
Translate Between GTL/GTL+ Signal Levels
and LVTTL Logic Levels
– 1000-V Charged-Device Model (C101)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Support Mixed-Mode Signal Operation on
All Ports (5-V Input/Output Voltages With
3.3-V V
)
Package Options Include Plastic Thin
Shrink Small-Outline (DGG) and Ceramic
Quad Flat (HV) Packages
CC
I
Supports Partial-Power-Down-Mode
off
Operation
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors on A Port
description
The ’GTL16923 devices are 18-bit registered bus transceivers that provide LVTTL-to-GTL/GTL+ and
GTL/GTL+-to-LVTTL signal-level translation. They are partitioned as two 9-bit transceivers with individual
output-enable controls and contain D-type flip-flops for temporary storage of data flowing in either direction. The
devices provide an interface between cards operating at LVTTL logic levels and a backplane operating at
GTL/GTL+ signal levels. Higher-speed operation is a direct result of the reduced output swing (<1 V), reduced
input threshold levels, and output edge control (OEC ).
The user has the flexibility of using these devices at either GTL (V = 1.2 V and V
= 0.8 V) or the preferred
TT
REF
higher noise margin GTL+ (V = 1.5 V and V
= 1 V) signal levels. GTL+ is the Texas Instruments derivative
TT
REF
of the Gunning transceiver logic (GTL) JEDEC standard JESD 8-3. The B port normally operates at GTL or
GTL+ signal levels, while the A-port and control inputs are compatible with LVTTL logic levels. All inputs can
be driven from either 3.3-V or 5-V devices which allows use in a mixed 3.3-V/5-V system environment. V
is the reference input voltage for the B port.
REF
Data flow in each direction is controlled by the output-enable (OEABandOEBA) and clock(CLKABandCLKBA)
inputs. The clock-enable (CEAB and CEBA) inputs are used to enable or disable the clock for all 18 bits at a
time. However, OEAB and OEBA are designed to control each 9-bit transceiver independently, which makes
the device more versatile.
For A-to-B data flow, the device operates on the low-to-high transition of CLKAB if CEAB is low. When OEAB
is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for
B to A is similar to that of A to B but uses OEBA, CLKBA, and CEBA.
These devices are fully specified for partial-power-down applications using I . The I circuitry disables the
off
off
outputs, preventing damaging current backflow through the devices when they are powered down.
Active bus-hold circuitry holds unused or undriven LVTTL inputs at a valid logic state. Use of pullup or pulldown
resistors with the bus-hold circuitry is not recommended.
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54GTL16923 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74GTL16923 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and OEC are trademarks of Texas Instruments Incorporated.
Copyright 1999, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
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