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SN74GTL2003 PDF预览

SN74GTL2003

更新时间: 2024-11-26 12:21:51
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德州仪器 - TI /
页数 文件大小 规格书
20页 652K
描述
8-BIT BIDIRECTIONAL LOW-VOLTAGE TRANSLATOR

SN74GTL2003 数据手册

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SN74GTL2003  
www.ti.com  
SCDS305 FEBRUARY 2011  
8-BIT BIDIRECTIONAL LOW-VOLTAGE TRANSLATOR  
Check for Samples: SN74GTL2003  
1
FEATURES  
APPLICATIONS  
Bidirectional or Unidirectional Applications  
Requiring Voltage-Level Translation From Any  
Voltage (1 V to 5 V) to Any Voltage (1 V to 5 V)  
Low Voltage Processor I2C Port Translation to  
3.3-V and/or 5-V I2C Bus Signal Levels  
Provides Bidirectional Voltage Translation  
With No Direction Control Required  
Allows Voltage Level Translation From 1 V up  
to 5 V  
Provides Direct Interface With GTL, GTL+,  
LVTTL/TTL, and 5-V CMOS Levels  
GTL/GTL+ Translation to LVTTL/TTL Signal  
Levels  
Low On-State Resistance Between Input and  
Output Pins (Sn/Dn)  
QFN PACKAGE  
(TOP VIEW)  
PW PACKAGE  
(TOP VIEW)  
terminal 1  
index area  
Supports Hot Insertion  
GND  
G
D
1
2
20  
19  
REF  
No Power Supply Required Will Not Latch Up  
5-V-Tolerant Inputs  
S
REF  
REF  
S
REF  
D
REF  
19  
18  
17  
16  
15  
14  
13  
12  
2
3
4
5
6
7
8
9
18 D1  
S1  
S2  
S3  
S4  
S5  
S6  
S7  
S8  
3
D2  
17  
4
S1  
S2  
S3  
S4  
S5  
S6  
S7  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
Low Standby Current  
16  
5
D3  
D4  
15  
6
Flow-Through Pinout for Ease of Printed  
Circuit Board Trace Routing  
7
D5  
D6  
D7  
D8  
14  
13  
8
ESD Performance Tested Per JESD 22  
9
12  
11  
2000-V Human-Body Model  
(A114-B, Class II)  
10  
1000-V Charged-Device Model (C101)  
DESCRIPTION/ORDERING INFORMATION  
The SN74GTL2003 provides eight NMOS pass transistors (Sn and Dn) with a common gate (GREF) and a  
reference transistor (SREF and DREF). The low ON-state resistance of the switch allows connections to be made  
with minimal propagation delay. With no direction control pin required, the device allows bidirectional voltage  
translations any voltage (1 V to 5 V) to any voltage (1 V to 5 V).  
When the Sn or Dn port is LOW, the clamp is in the ON state and a low-resistance connection exists between  
the Sn and Dn ports. Assuming the higher voltage is on the Dn port, when the Dn port is HIGH, the voltage on  
the Sn port is limited to the voltage set by the reference transistor (SREF). When the Sn port is HIGH, the Dn port  
is pulled to VCC by the pullup resistors.  
All transistors in the SN74GTL2003 have the same electrical characteristics, and there is minimal deviation from  
one output to another in voltage or propagation delay. This offers superior matching over discrete transistor  
voltage-translation solutions where the fabrication of the transistors is not symmetrical. With all transistors being  
identical, the reference transistor (SREF/DREF) can be located on any of the other eight matched Sn/Dn  
transistors, allowing for easier board layout. The translator transistors with integrated ESD circuitry provides  
excellent ESD protection.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
© 2011, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  

SN74GTL2003 替代型号

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