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SN74GTL16622ADGG PDF预览

SN74GTL16622ADGG

更新时间： 2024-11-05 22:53:35
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路电视光电二极管信息通信管理
页数 文件大小 规格书
10页 165K
描述
18-BIT LVTTL-TO-GTL/GTL BUS TRANSCEIVERS

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SN74GTL16622ADGG 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：PLASTIC, TSSOP-64针数：64
Reach Compliance Code：compliantHTS代码：8542.39.00.01
Factory Lead Time：1 week风险等级：5.56
Is Samacsys：N系列：GTL/TVC
JESD-30 代码：R-PDSO-G64JESD-609代码：e4
长度：17 mm负载电容（CL）：50 pF
逻辑集成电路类型：REGISTERED BUS TRANSCEIVER湿度敏感等级：1
位数：9功能数量：2
端口数量：2端子数量：64
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260最大电源电流（ICC）：60 mA
传播延迟（tpd）：5.7 ns认证状态：Not Qualified
座面最大高度：1.2 mm最大供电电压 (Vsup)：3.45 V
最小供电电压 (Vsup)：3.15 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：BICMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：6.1 mmBase Number Matches：1

SN74GTL16622ADGG 数据手册

 浏览型号SN74GTL16622ADGG的Datasheet PDF文件第2页浏览型号SN74GTL16622ADGG的Datasheet PDF文件第3页浏览型号SN74GTL16622ADGG的Datasheet PDF文件第4页浏览型号SN74GTL16622ADGG的Datasheet PDF文件第5页浏览型号SN74GTL16622ADGG的Datasheet PDF文件第6页浏览型号SN74GTL16622ADGG的Datasheet PDF文件第7页 
SN54GTL16622A, SN74GTL16622A  
18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVERS  
SCBS673D – AUGUST 1996 – REVISED DECEMBER 1999  
SN74GTL16622A . . . DGG PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
Widebus Family  
D-Type Flip-Flops With Qualified Storage  
Enable  
OEAB  
1A1  
GND  
1A2  
1A3  
GND  
CLKAB  
1CEAB  
1CEBA  
1B1  
GND  
1B2  
1
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
2
Translate Between GTL/GTL+ Signal Levels  
and LVTTL Logic Levels  
3
4
Support Mixed-Mode (3.3 V and 5 V) Signal  
Operation on A-Port and Control Inputs  
5
6
I
Supports Partial-Power-Down Mode  
V
1B3  
7
CC  
off  
Operation  
1A4  
GND  
1A5  
1A6  
GND  
1A7  
1A8  
GND  
1A9  
2A1  
GND  
2A2  
2A3  
GND  
2A4  
2A5  
GND  
2A6  
V
8
CC  
1B4  
1B5  
1B6  
GND  
1B7  
1B8  
GND  
1B9  
2B1  
GND  
2B2  
2B3  
GND  
2B4  
2B5  
2B6  
9
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors on A Port  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
– 1000-V Charged-Device Model (C101)  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
Distributed V  
Minimizes High-Speed Noise  
and GND-Pin Configuration  
CC  
Package Options Include Plastic Thin  
Shrink Small-Outline (DGG) and Ceramic  
Quad Flat (HV) Packages  
V
description  
REF  
V
2B7  
2B8  
GND  
2B9  
2CEBA  
2CEAB  
CLKBA  
CC  
The  
’GTL16622A  
devices  
are  
18-bit  
GND  
2A7  
2A8  
GND  
2A9  
registered bus transceivers that provide  
LVTTL-to-GTL/GTL+ and GTL/GTL+-to-LVTTL  
signal-level translation. They are partitioned as  
two separate 9-bit transceivers with individual  
clock-enable controls and contain D-type  
flip-flops for temporary storage of data flowing in  
either direction. The devices provide an interface  
between cards operating at LVTTL logic levels  
and a backplane operating at GTL/GTL+ signal  
levels. Higher speed operation is a direct result of  
the reduced output swing (<1 V), reduced input  
threshold levels, and output edge control  
(OEC ).  
OEBA  
The user has the flexibility of using this device at either GTL (V = 1.2 V and V  
= 0.8 V) or the preferred  
TT  
REF  
higher noise margin GTL+ (V = 1.5 V and V  
= 1 V) signal levels. GTL+ is the Texas Instruments derivative  
TT  
REF  
of the Gunning transceiver logic (GTL) JEDEC standard JESD 8-3. The B port normally operates at GTL or  
GTL+ signal levels, while the A-port and control inputs are compatible with LVTTL logic levels and are 5-V  
tolerant. V  
is the reference input voltage for the B port.  
REF  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
OEC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...10

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