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SN74GTL16622ADGGE4 PDF预览

SN74GTL16622ADGGE4

更新时间： 2024-11-06 14:38:35
品牌 Logo 应用领域
德州仪器 - TI 信息通信管理光电二极管输出元件逻辑集成电路电视
页数 文件大小 规格书
13页 452K
描述
GTL/TVC SERIES, DUAL 9-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO64, PLASTIC, TSSOP-64

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SN74GTL16622ADGGE4 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP,针数：64
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.58Is Samacsys：N
系列：GTL/TVCJESD-30 代码：R-PDSO-G64
JESD-609代码：e4长度：17 mm
负载电容（CL）：50 pF逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
湿度敏感等级：1位数：9
功能数量：2端口数量：2
端子数量：64最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
最大电源电流（ICC）：60 mA传播延迟（tpd）：5.7 ns
认证状态：Not Qualified座面最大高度：1.2 mm
最大供电电压 (Vsup)：3.45 V最小供电电压 (Vsup)：3.15 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：BICMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：6.1 mm
Base Number Matches：1

SN74GTL16622ADGGE4 数据手册

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SN74GTL16622A  
18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVER  
www.ti.com  
SCBS673F–AUGUST 1996–REVISED APRIL 2005  
FEATURES  
DGG PACKAGE  
(TOP VIEW)  
•
•
•
•
•
•
•
Member of Texas Instruments Widebus™  
Family  
OEAB  
1A1  
CLKAB  
1CEAB  
1CEBA  
1B1  
GND  
1B2  
1
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
OEC™ Circuitry Improves Signal Integrity and  
Reduces Electromagnetic Interference  
2
GND  
1A2  
1A3  
3
D-Type Flip-Flops With Qualified Storage  
Enable  
4
5
Translates Between GTL/GTL+ Signal Levels  
and LVTTL Logic Levels  
GND  
6
V
CC  
1B3  
7
Supports Mixed-Mode (3.3 V and 5 V) Signal  
Operation on A-Port and Control Inputs  
1A4  
GND  
1A5  
1A6  
GND  
1A7  
1A8  
GND  
1A9  
2A1  
GND  
2A2  
2A3  
GND  
2A4  
2A5  
GND  
2A6  
V
8
CC  
1B4  
1B5  
1B6  
GND  
1B7  
1B8  
GND  
1B9  
2B1  
GND  
2B2  
2B3  
GND  
2B4  
2B5  
2B6  
9
Ioff Supports Partial-Power-Down Mode  
Operation  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
Bus Hold on Data Inputs Eliminates the Need  
for External Pullup/Pulldown Resistors on  
A Port  
•
•
•
Distributed VCC and GND Pins Minimize  
High-Speed Noise  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
– 1000-V Charged-Device Model (C101)  
DESCRIPTION/ORDERING INFORMATION  
V
REF  
V
CC  
2B7  
2B8  
GND  
2B9  
The SN74GTL16622A is an 18-bit registered bus  
transceiver that provides LVTTL-to-GTL/GTL+ and  
GTL/GTL+-to-LVTTL signal-level translation. This  
device is partitioned as two separate 9-bit  
transceivers with individual clock-enable controls and  
contains D-type flip-flops for temporary storage of  
data flowing in either direction. This device provides  
an interface between cards operating at LVTTL logic  
levels and a backplane operating at GTL/GTL+ signal  
levels. Higher-speed operation is a direct result of the  
reduced output swing (<1 V), reduced input threshold  
levels, and OEC™ circuitry.  
GND  
2A7  
2A8  
GND 30  
2A9 31  
35 2CEBA  
34 2CEAB  
OEBA  
CLKBA  
32  
33  
The user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or the preferred  
higher noise margin GTL+ (VTT = 1.5 V and VREF = 1 V) signal levels. GTL+ is the Texas Instruments derivative  
of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The B port normally operates at GTL or  
GTL+ signal levels, while the A-port and control inputs are compatible with LVTTL logic levels and are 5-V  
tolerant. VREF is the reference input voltage for the B port.  
Data flow in each direction is controlled by the output-enable (OEAB and OEBA) and clock (CLKAB and CLKBA)  
inputs. The clock-enable (CEAB and CEBA) inputs control each 9-bit transceiver independently, which makes the  
device more versatile.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus, OEC are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1996–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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