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SN74F86NSRG4 PDF预览

SN74F86NSRG4

更新时间： 2024-09-14 15:52:11
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 栅光电二极管逻辑集成电路石英晶振
页数 文件大小 规格书
9页 277K
描述
XOR Gate, F/FAST Series, 4-Func, 2-Input, TTL, PDSO14, GREEN, PLASTIC, SOP-14

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SN74F86NSRG4 技术参数

生命周期：Contact Manufacturer包装说明：GREEN, PLASTIC, SOP-14
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.63系列：F/FAST
JESD-30 代码：R-PDSO-G14长度：10.2 mm
逻辑集成电路类型：XOR GATE功能数量：4
输入次数：2端子数量：14
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
传播延迟（tpd）：8 ns座面最大高度：2 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：TTL温度等级：COMMERCIAL
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL宽度：5.3 mm
Base Number Matches：1

SN74F86NSRG4 数据手册

 浏览型号SN74F86NSRG4的Datasheet PDF文件第2页浏览型号SN74F86NSRG4的Datasheet PDF文件第3页浏览型号SN74F86NSRG4的Datasheet PDF文件第4页浏览型号SN74F86NSRG4的Datasheet PDF文件第5页浏览型号SN74F86NSRG4的Datasheet PDF文件第6页浏览型号SN74F86NSRG4的Datasheet PDF文件第7页 
SN54F86, SN74F86  
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES  
SDFS019B – JANUARY 1989 – REVISED JANUARY 1997  
SN54F86 . . . J PACKAGE  
SN74F86 . . . D OR N PACKAGE  
(TOP VIEW)  
Package Options Include Plastic  
Small-Outline (D) Packages, Ceramic Chip  
Carriers (FK), and Standard Plastic (N) and  
Ceramic (J) 300-mil DIPs  
1A  
1B  
1Y  
2A  
2B  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
4B  
4A  
4Y  
3B  
3A  
3Y  
description  
These devices contain four independent 2-input  
exclusive-OR gates. They perform the Boolean  
function Y = A B or Y = AB + AB in positive logic.  
2Y  
GND  
8
A common application is as a true/complement  
element. If one of the inputs is low, the other input  
is reproduced in true form at the output. If one of  
the inputs is high, the signal on the other input is  
reproduced inverted at the output.  
SN54F86 . . . FK PACKAGE  
(TOP VIEW)  
The SN54F86 is characterized for operation over  
the full military temperature range of –55°C to  
125°C. The SN74F86 is characterized for  
operation from 0°C to 70°C.  
3
2
1
20 19  
18  
1Y  
NC  
2A  
4
5
6
7
8
4A  
NC  
4Y  
NC  
3B  
17  
16  
15  
14  
FUNCTION TABLE  
(each gate)  
NC  
2B  
9 10 11 12 13  
INPUTS  
OUTPUT  
Y
A
B
L
L
L
L
H
H
L
H
L
NC – No internal connection  
H
H
H
†
logic symbol  
1
= 1  
1A  
2
3
1Y  
1B  
4
2A  
5
6
2Y  
2B  
9
3A  
8
10  
3Y  
3B  
4A  
4B  
12  
13  
11  
4Y  
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.  
Pin numbers shown are for the D, J, and N packages.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

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