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SN74F163AN3 PDF预览

SN74F163AN3

更新时间: 2024-09-16 04:51:15
品牌 Logo 应用领域
德州仪器 - TI 计数器
页数 文件大小 规格书
14页 373K
描述
SYNCHRONOUS 4-BIT BINARY COUNTER

SN74F163AN3 数据手册

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SN74F163A  
SYNCHRONOUS 4-BIT BINARY COUNTER  
SDFS088A – MARCH 1987 – REVISED AUGUST 2001  
D, DB, OR N PACKAGE  
(TOP VIEW)  
Internal Look-Ahead Circuitry for Fast  
Counting  
Carry Output for N-Bit Cascading  
V
RCO  
Q
CLR  
CLK  
A
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CC  
Fully Synchronous Operation for Counting  
A
description  
Q
B
Q
B
C
D
C
This synchronous, presettable, 4-bit binary  
counter has internal carry look-ahead circuitry  
for use in high-speed counting designs.  
Synchronous operation is provided by having all  
flip-flops clocked simultaneously so that the  
outputs change coincident with each other when  
Q
D
ENT  
ENP  
GND  
LOAD  
so instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the  
output counting spikes that normally are associated with asynchronous (ripple-clock) counters. However,  
counting spikes can occur on the ripple-carry (RCO) output. A buffered clock (CLK) input triggers the four  
flip-flops on the rising (positive-going) edge of CLK.  
This counter is fully programmable. That is, it can be preset to any number between 0 and 15. Because  
presettingissynchronous, alowlogiclevelattheload(LOAD)inputdisablesthecounterandcausestheoutputs  
to agree with the setup data after the next clock pulse, regardless of the levels of ENP and ENT.  
Theclearfunctionissynchronous, andalowlogiclevelattheclear(CLR)inputsetsallfouroftheflip-flopoutputs  
to low after the next low-to-high transition of the clock, regardless of the levels of ENP and ENT. This  
synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum  
count desired. The active-low output of the gate used for decoding is connected to the clear input to  
synchronously clear the counter to 0000 (LLLL).  
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications, without  
additional gating. This function is implemented by the ENP and ENT inputs and an RCO output. Both ENP and  
ENT must be high to count, and ENT is fed forward to enable RCO. RCO, thus enabled, produces a  
high-logic-levelpulse while the count is 15 (HHHH). The high-logic-level overflow ripple-carry pulse can be used  
to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK.  
The SN74F163A features a fully independent clock circuit. Changes at ENP, ENT, or LOAD that modify the  
operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter  
(whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the setup and hold  
times.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP – N  
SOIC – D  
SSOP – DB  
Tube  
SN74F163AN  
SN74F163AD  
SN74F163ADR  
SN74F163ADBR  
SN74F163AN  
Tube  
0°C to 70°C  
F163A  
Tape and reel  
Tape and reel  
F163A  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2001, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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