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SN74F169DRG4 PDF预览

SN74F169DRG4

更新时间： 2024-09-16 15:52:11
品牌 Logo 应用领域
德州仪器 - TI 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
14页 437K
描述
F/FAST SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDSO16, PLASTIC, SO-16

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SN74F169DRG4 技术参数

是否Rohs认证：符合生命周期：Obsolete
零件包装代码：SOIC包装说明：SOP, SOP16,.25
针数：16Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.65
Is Samacsys：N其他特性：TCO OUTPUT
计数方向：BIDIRECTIONAL系列：F/FAST
JESD-30 代码：R-PDSO-G16长度：9.9 mm
负载电容（CL）：50 pF负载/预设输入：YES
逻辑集成电路类型：BINARY COUNTER最大频率@ Nom-Sup：90000000 Hz
最大I（ol）：0.02 A工作模式：SYNCHRONOUS
位数：4功能数量：1
端子数量：16最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP16,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5 V最大电源电流（ICC）：52 mA
传播延迟（tpd）：13 ns认证状态：Not Qualified
座面最大高度：1.75 mm子类别：Counters
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：TTL温度等级：COMMERCIAL
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
触发器类型：POSITIVE EDGE宽度：3.9 mm
最小 fmax：90 MHzBase Number Matches：1

SN74F169DRG4 数据手册

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SDFS089 − MARCH 1987 − REVISED OCTOBER 1993  
D OR N PACKAGE  
(TOP VIEW)  
• Fully Synchronous Operation for Counting  
and Programming  
• Internal Look-Ahead Circuitry for Fast  
V
RCO  
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CLK  
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• Carry Output for N-Bit Cascading  
• Fully Independent Clock Circuit  
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• Package Options Include Plastic  
Small-Outline Packages and Standard  
Plastic 300-mil DIPs  
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description  
This synchronous, presettable, 4-bit up/down binary counter features an internal carry look-ahead circuitry for  
cascading in high-speed counting applications. Synchronous operation is provided by having all flip-flops  
clocked simultaneously so that the outputs change coincident with each other when so instructed by the  
count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting  
spikes that are normally associated with asynchronous (ripple-clock) counters. A buffered clock (CLK) input  
triggers the four flip-flops on the rising (positive-going) edge of the clock waveform.  
This counter is fully programmable; that is, it may be preset to any number between 0 and its maximum count.  
The load-input circuitry allows loading with the carry-enable output of cascaded counters. As loading is  
synchronous, setting up a low level at the load (LOAD) input disables the counter and causes the outputs to  
agree with the data inputs after the next clock pulse.  
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous application without  
additional gating. Instrumental in accomplishing this function are two count-enable (ENP, ENT) inputs and a  
ripple-carry (RCO) output. Both ENP and ENT must be low to count. The direction of the count is determined  
by the level of the up/down (U/D) input. When U/D is high, the counter counts up; when low, it counts down. Input  
ENT is fed forward to enable the RCO. RCO thus enabled will produce a low-level pulse while the count is zero  
(all inputs low) counting down or maximum (9 or 15) counting up. This low-level overflow ripple-carry pulse can  
be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed regardless of the level  
of the clock input. All inputs are diode clamped to minimize transmission-line effects, thereby simplifying system  
design.  
The SN74F169 features a fully independent clock circuit. Changes at control inputs (ENP, ENT, LOAD or U/D)  
that will modify the operating mode have no effect on the contents of the counter until clocking occurs. The  
function of the counter (whether enabled, disabled, loading, or counting) will be dictated solely by the conditions  
meeting the setup and hold times.  
The SN74F169 is characterized for operation from 0°C to 70°C.  
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Copyright 1993, Texas Instruments Incorporated  
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2−1  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
1234567...14

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