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SN74CBTLV3245ADGVRE4 PDF预览

SN74CBTLV3245ADGVRE4

更新时间： 2024-09-16 15:52:11
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
11页 342K
描述
IC,BUS SWITCH,CMOS,TSSOP,20PIN,PLASTIC

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SN74CBTLV3245ADGVRE4 技术参数

生命周期：Obsolete包装说明：TSSOP, TSSOP20,.25,16
Reach Compliance Code：unknown风险等级：5.84
JESD-30 代码：R-PDSO-G20长度：5 mm
逻辑集成电路类型：BUS DRIVER端子数量：20
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP20,.25,16封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH电源：2.5/3.3 V
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：Bus Driver/Transceivers表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.4 mm
端子位置：DUAL宽度：4.4 mm
Base Number Matches：1

SN74CBTLV3245ADGVRE4 数据手册

 浏览型号SN74CBTLV3245ADGVRE4的Datasheet PDF文件第2页浏览型号SN74CBTLV3245ADGVRE4的Datasheet PDF文件第3页浏览型号SN74CBTLV3245ADGVRE4的Datasheet PDF文件第4页浏览型号SN74CBTLV3245ADGVRE4的Datasheet PDF文件第5页浏览型号SN74CBTLV3245ADGVRE4的Datasheet PDF文件第6页浏览型号SN74CBTLV3245ADGVRE4的Datasheet PDF文件第7页 
SN74CBTLV3245A  
LOW-VOLTAGE OCTAL FET BUS SWITCH  
www.ti.com  
SCDS034L–JULY 1997–REVISED MARCH 2005  
FEATURES  
•
•
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
•
•
•
•
Standard '245-Type Pinout  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
5-Ω Switch Connection Between Two Ports  
Rail-to-Rail Switching on Data I/O Ports  
Ioff Supports Partial-Power-Down Mode  
Operation  
DBQ, DGV, DW, OR PW PACKAGE  
(TOP VIEW)  
RGY PACKAGE  
(TOP VIEW)  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
NC  
A1  
A2  
V
CC  
OE  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
1
20  
19  
18  
17  
16  
15  
14  
13  
12  
2
3
4
5
6
7
8
9
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
OE  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
A3  
A4  
A5  
A6  
A7  
A8  
GND  
10  
11  
NC - No internal connection  
NC - No internal connection  
DESCRIPTION/ORDERING INFORMATION  
The SN74CBTLV3245A provides eight bits of high-speed bus switching in a standard '245 device pinout. The low  
on-state resistance of the switch allows connections to be made with minimal propagation delay.  
The device is organized as one 8-bit switch. When output enable (OE) is low, the 8-bit bus switch is on, and port  
A is connected to port B. When OE is high, the switch is open, and the high-impedance state exists between the  
two ports.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging  
current will not backflow through the device when it is powered down. The device has isolation during power off.  
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
SN74CBTLV3245ARGYR  
SN74CBTLV3245ADW  
TOP-SIDE MARKING  
QFN – RGY  
SOIC – DW  
Tape and reel  
CL245A  
Tube  
CBTLV3245A  
Tape and reel  
Tape and reel  
Tape and reel  
Tape and reel  
SN74CBTLV3245ADWR  
SN74CBTLV3245ADBQR  
SN74CBTLV3245APWR  
SN74CBTLV3245ADGVR  
–40°C to 85°C  
SSOP (QSOP) – DBQ  
TSSOP – PW  
CBTLV3245A  
CL245A  
TVSOP – DGV  
CL245A  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1997–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...11

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