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SN74CBTLV3125_09 PDF预览

SN74CBTLV3125_09

更新时间： 2024-09-15 11:54:23
品牌 Logo 应用领域
德州仪器 - TI 开关
页数 文件大小 规格书
19页 834K
描述
Low-VOLTAGE QUADRUPLE FET BUS SWITCH

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SN74CBTLV3125_09 数据手册

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SCDS037J − DECEMBER 1997 − REVISED OCTOBER 2003  
D
D
D
Standard ’125-Type Pinout  
D
D
I
Supports Partial-Power-Down Mode  
off  
Operation  
5-Ω Switch Connection Between Two Ports  
Rail-to-Rail Switching on Data I/O Ports  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
D, DGV, NS, OR PW PACKAGE  
(TOP VIEW)  
RGY PACKAGE  
(TOP VIEW)  
DBQ PACKAGE  
(TOP VIEW)  
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14  
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1
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16  
15  
14  
13  
12  
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10  
9
V
4OE  
4A  
4B  
3OE  
3A  
3B  
NC  
1OE  
1A  
1B  
2OE  
2A  
1OE  
1A  
1B  
2OE  
2A  
2B  
V
CC  
4OE  
CC  
1
14  
4A  
4B  
3OE  
3A  
3B  
1A  
1B  
13 4OE  
12 4A  
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10  
9
2OE  
2A  
4B  
3OE  
3A  
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2B  
GND  
GND  
2B  
NC  
7
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NC − No internal connection  
description/ordering information  
The SN74CBTLV3125 quadruple FET bus switch features independent line switches. Each switch is disabled  
when the associated output-enable (OE) input is high.  
This device is fully specified for partial-power-down applications using I . The I feature ensures that  
off  
off  
damaging current will not backflow through the device when it is powered down. The device has isolation during  
power off.  
To ensure the high-impedance state during power up or power down, OE should be tied to V  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through a pullup  
CC  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
QFN − RGY  
SOIC − D  
Tape and reel  
SN74CBTLV3125RGYR  
SN74CBTLV3125D  
CL125  
Tube  
CBTLV3125  
Tape and reel  
Tape and reel  
SN74CBTLV3125DR  
SN74CBTLV3125NSR  
SN74CBTLV3125DBQR  
SN74CBTLV3125PWR  
SN74CBTLV3125DGVR  
−40°C to 85°C SOP − NS  
CBTLV3125  
CL125  
SSOP (QSOP) − DBQ Tape and reel  
TSSOP − PW  
TVSOP − DGV  
Tape and reel  
Tape and reel  
CL125  
CL125  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
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Copyright 2003, Texas Instruments Incorporated  
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ꢢ ꢦ ꢣ ꢢꢛ ꢜꢰ ꢞꢝ ꢡ ꢩꢩ ꢧꢡ ꢟ ꢡ ꢠ ꢦ ꢢ ꢦ ꢟ ꢣ ꢫ  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
1234567...19

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