SN74BCT29834

更新时间： 2024-11-13 22:40:23

品牌	Logo	应用领域
德州仪器 - TI		总线收发器
页数	文件大小	规格书
7页	101K
描述
8-BIT TO 9-BIT PARITY BUS TRANSCEIVER

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数据手册

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SN74BCT29834 数据手册

SN74BCT29834

8-BIT TO 9-BIT PARITY BUS TRANSCEIVER

SCBS256 – SEPTEMBER 1987 – REVISED NOVEMBER 1993

DW OR NT PACKAGE

(TOP VIEW)

• BiCMOS Process With TTL Inputs and

Outputs

• BiCMOS Design Reduces Standby Current

OEA

• Flow-Through Pinout (All Inputs on

Opposite Side From Outputs)

• Functionally Equivalent to SN74ALS29834

and AMD Am29834

• High-Speed Bus Transceiver With Parity

Generator/Checker

• Parity-Error Flag With Open-Collector

Output

ERR

CLR

PARITY

OEB

• Available Register For Storage of the

Parity-Error Flag

GND 12

13 CLK

• Package Options Include Plastic

Small-Outline (DW) Packages and Standard

Plastic 300-mil DIPs (NT)

description

The SN74BCT29834 is an 8-bit to 9-bit parity transceiver designed for asynchronous communication between

data buses. When data is transmitted from the A to B bus, a parity bit is generated. When data is transmitted

from the B to A bus with its corresponding parity bit, the parity-error (ERR) output will indicate whether or not

an error in the B data has occurred. The output-enable (OEA, OEB) inputs can be used to disable the device

so that the buses are effectively isolated.

A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports

with an open-collector parity-error flag (ERR). ERR is clocked into the register on the rising edge of the CLK

input. The error flag register is cleared with a low pulse on the clear (CLR) input. When both OEA and OEB are

low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced

error condition which gives the designer more system diagnostic capability. The SN74BCT29834 provides

inverting logic.

The SN74BCT29834 is characterized for operation from 0°C to 70°C.

FUNCTION TABLE

INPUTS

CLK

OUTPUT AND I/O

†

∑ of L’s

FUNCTION

∑ of H’s

‡

PARITY

ERR

OEB

OEA

CLR

Odd

Even

A data to B bus and generate parity

Odd

Even

↑

B data to A bus and check parity

Clear error-flag register

No↑

↑

Odd

Even

Isolation

↑

Odd

Even

A data to B bus and generate inverted

parity

NA = not applicable, NC = no change, X = don’t care

†

‡

Summation of high-level inputs includes PARITY along with Bi inputs.

Output states shown assume the ERR output was previously high.

In this mode, the ERR output, when enabled, shows inverted parity of the A bus.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

2–1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7

中文翻译

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与SN74BCT29834相关器件

型号	品牌	获取价格	描述	数据表
SN74BCT29834_11	TI	获取价格	8-BIT TO 9-BIT PARITY BUS TRANSCEIVER
SN74BCT29834DW	TI	获取价格	8-BIT TO 9-BIT PARITY BUS TRANSCEIVER
SN74BCT29834DW-00	TI	获取价格	BCT/FBT SERIES, 8-BIT TRANSCEIVER, INVERTED OUTPUT, PDSO24
SN74BCT29834DWR	TI	获取价格	暂无描述
SN74BCT29834FN	TI	获取价格	IC,BUS TRANSCEIVER,SINGLE,8-BIT,BICMOS-TTL,LDCC,28PIN,PLASTIC
SN74BCT29834NT	TI	获取价格	8-BIT TO 9-BIT PARITY BUS TRANSCEIVER
SN74BCT29834NT-10	TI	获取价格	BCT/FBT SERIES, 8-BIT TRANSCEIVER, INVERTED OUTPUT, PDIP24
SN74BCT29841	TI	获取价格	10-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN74BCT29841DW	TI	获取价格	暂无描述
SN74BCT29841DW	ROCHESTER	获取价格	BCT/FBT SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24, PLASTIC, SO-24

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