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SN74BCT29844DW PDF预览

SN74BCT29844DW

更新时间: 2024-11-14 12:22:31
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器锁存器逻辑集成电路光电二极管信息通信管理
页数 文件大小 规格书
6页 99K
描述
9-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OURPUTS

SN74BCT29844DW 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:PLASTIC, SOIC-24针数:24
Reach Compliance Code:not_compliant风险等级:5.92
Is Samacsys:N其他特性:WITH CLEAR AND PRESET
系列:BCT/FBTJESD-30 代码:R-PDSO-G24
长度:15.4 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.048 A
位数:9功能数量:1
端口数量:2端子数量:24
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE输出极性:INVERTED
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP24,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 VProp。Delay @ Nom-Sup:15 ns
传播延迟(tpd):8.2 ns认证状态:Not Qualified
座面最大高度:2.65 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:BICMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.5 mmBase Number Matches:1

SN74BCT29844DW 数据手册

 浏览型号SN74BCT29844DW的Datasheet PDF文件第2页浏览型号SN74BCT29844DW的Datasheet PDF文件第3页浏览型号SN74BCT29844DW的Datasheet PDF文件第4页浏览型号SN74BCT29844DW的Datasheet PDF文件第5页浏览型号SN74BCT29844DW的Datasheet PDF文件第6页 
ꢀꢁꢂ ꢃ ꢄ ꢅꢆ ꢇꢈ ꢉꢃꢃ  
ꢈ ꢊꢄꢋ ꢆꢌ ꢄꢍꢀ ꢊꢋꢁꢆ ꢎꢏ ꢐꢑꢅꢎ ꢌꢒꢊꢆ ꢓꢔ ꢎ ꢌꢕ ꢑꢆꢅ ꢖ  
ꢗ ꢋꢆ ꢖꢌ ꢘ ꢊꢀꢆꢑꢆ ꢎꢌ ꢙꢍ ꢆꢔ ꢍꢆ ꢀ  
SCBS077A − SEPTEMBER 1991 − REVISED NOVEMBER 1993  
DW OR NT PACKAGE  
(TOP VIEW)  
State-of-the-Art BiCMOS Design  
Significantly Reduces I  
CCZ  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883C, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
1
2
3
4
5
6
7
8
9
24  
23 1Q  
22 2Q  
21 3Q  
20 4Q  
19 5Q  
18 6Q  
17 7Q  
16 8Q  
15 9Q  
14 PRE  
13 LE  
Package Options Include Plastic  
Small-Outline (DW) Packages and Standard  
Plastic 300-mil DIPs (NT)  
description  
The SN74BCT29844 features 3-state outputs  
designed specifically for driving highly capacitive  
or relatively low-impedance loads. It is particularly  
suitable for implementing wider buffer registers,  
I/O ports, bidirectional bus drivers with parity, and  
working registers.  
9D 10  
CLR 11  
GND 12  
The nine latches are transparent D-type latches. When the latch-enable (LE) input is high, the Q outputs are  
complementary to the inverting data (D) inputs.  
A buffered output-enable (OE) input can be used to place the nine outputs in either a normal logic state (high  
or low level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus  
lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without  
need for interface or pull-up components.  
The output enable (OE) does not affect the internal operation of the flip-flops. Old data can be retained or new  
data can be entered while the outputs are in the high-impedance state.  
The SN74BCT29844 is characterized for operation from 0°C to 70°C.  
FUNCTION TABLE  
INPUTS  
OUTPUT  
Q
PRE  
L
CLR  
X
OE  
L
LE  
X
D
X
X
L
H
L
H
L
L
X
H
H
L
H
H
L
H
L
H
H
L
H
X
X
H
H
L
Q
0
X
X
H
X
Z
ꢆꢥ  
Copyright 1993, Texas Instruments Incorporated  
ꢡ ꢥ ꢢ ꢡꢚ ꢛꢯ ꢝꢜ ꢠ ꢨꢨ ꢦꢠ ꢞ ꢠ ꢟ ꢥ ꢡ ꢥ ꢞ ꢢ ꢪ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  

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